Inventor profile of:

Ning CHEN

City:

San Jose, California

Country:

United States

Published Applications:

47

Last publication date:

2026-05-28

Top Assignees for applications by Ning CHEN

The entities that hold a legal rights for patent applications filed by inventor CHEN Ning:

Recent patent applications by CHEN Ning

Ning CHEN from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-05-28
US20260147667A1
Physics

TRACKING HOST-PROVIDED METADATA IN A MEMORY SUB-SYSTEM

#2 | 2025-05-15
US20250156101A1
Physics

HYBRID WEAR LEVELING FOR IN-PLACE DATA REPLACEMENT MEDIA

#3 | 2024-05-02
US20240143231A1
Physics

CONSOLIDATING WRITE REQUEST IN CACHE MEMORY

#4 | 2023-08-10
US20230251927A1
Physics

Tracking host-provided metadata in a memory sub-system

#5 | 2023-03-30
US20230097187A1
Physics

HYBRID WEAR LEVELING FOR IN-PLACE DATA REPLACEMENT MEDIA

#6 | 2023-03-02
US20230069122A1
Physics

Using P2L mapping table to manage move operation

#7 | 2023-03-02
US20230067738A1
Physics

Tracking host-provided metadata in a memory sub-system

#8 | 2023-03-02
US20230067281A1
Physics

Consolidating write request in cache memory

#9 | 2023-01-19
US20230019910A1
Physics

Limiting hot-cold swap wear leveling

#10 | 2022-12-22
US20220404969A1
Physics

Maintenance operations for memory devices

#11 | 2022-09-29
US20220308767A1
Physics

Performing hybrid wear leveling operations based on a sub-total write counter

#12 | 2022-08-25
US20220269598A1
Physics

Wear leveling based on sub-group write counts in a memory sub-system

#13 | 2022-06-30
US20220206941A1
Physics

Maintaining data consistency in a memory sub-system that uses hybrid wear leveling operations

#14 | 2022-01-20
US20220019383A1
Physics

Unmap data pattern for coarse mapping memory sub-system

#15 | 2021-11-04
US20210342220A1
Physics

Generating error checking data for error detection during modification of data in a memory sub-system

#16 | 2021-09-02
US20210271544A1
Physics

Generating error checking data for error detection during modification of data in a memory sub-system

#17 | 2021-04-01
US20210096986A1
Physics

Maintaining data consistency in a memory subsystem that uses hybrid wear leveling operations

#18 | 2021-03-25
US20210089218A1
Physics

Performing hybrid wear leveling operations based on a sub-total write counter

#19 | 2021-03-11
US20210073068A1
Physics

Write buffer management

#20 | 2021-01-21
US20210019254A1
Physics

Wear leveling based on sub-group write counts in a memory sub-system

#21 | 2021-01-21
US20210019181A1
Physics

Internal management traffic regulation for memory sub-systems

#22 | 2021-01-21
US20210019088A1
Physics

Unmap data pattern for coarse mapping memory sub-system

#23 | 2021-01-21
US20210019058A1
Physics

Limiting hot-cold swap wear leveling

#24 | 2021-01-21
US20210019050A1
Physics

Maintenance operations for memory devices

#25 | 2021-01-14
US20210011800A1
Physics

Generating error checking data for error detection during modification of data in a memory sub-system

#26 | 2021-01-14
US20210011799A1
Physics

Generating error checking data for error detection during modification of data in a memory sub-system

#27 | 2020-11-12
US20200356283A1
Physics

Multi-level wear leveling for non-volatile memory

#28 | 2020-04-09
US20200110544A1
Physics

Performing hybrid wear leveling operations based on a sub-total write counter

#29 | 2020-03-12
US20200081828A1
Physics

Maintaining data consistency in a memory sub system that uses hybrid wear leveling operations

#30 | 2020-02-27
US20200065020A1
Physics

Hybrid wear leveling for in-place data replacement media

#31 | 2020-02-27
US20200065007A1
Physics

Multi-level wear leveling for non-volatile memory

#32 | 2020-01-23
US20200026595A1
Physics

Write buffer management

#33 | 2017-11-09
US20170322750A1
Physics

Systems and methods for latency based data recycling in a solid state memory system

#34 | 2016-12-08
US20160357485A1
Physics

Systems and methods for latency based data recycling in a solid state memory system

#35 | 2016-10-20
US20160308556A1
Electricity

Systems and methods for differential message scaling in a decoding process

#36 | 2016-04-21
US20160110116A1
Physics

Method to shorten hash chains in lempel-ziv compression of data with repetitive symbols

#37 | 2015-10-08
US20150286523A1
Physics

Systems and methods for differential message scaling in a decoding process

#38 | 2015-07-16
US20150199140A1
Physics

Interleaving codewords over multiple flash planes

#39 | 2015-06-25
US20150178149A1
Physics

Method to distribute user data and error correction data over different page types by leveraging error rate variations

#40 | 2015-04-23
US20150113205A1
Physics

Systems and methods for latency based data recycling in a solid state memory system

#41 | 2014-09-25
US20140286102A1
Physics

Method of optimizing solid state drive soft retry voltages

#42 | 2014-09-18
US20140266815A1
Electricity

Lempel-Ziv data compression with shortened hash chains based on repetitive patterns

#43 | 2014-06-26
US20140181617A1
Electricity

Management of non-valid decision patterns of a soft read retry operation

#44 | 2014-06-12
US20140164880A1
Physics

Error correction code rate management for nonvolatile memory

#45 | 2014-06-12
US20140164868A1
Physics

Flash memory read error recovery with soft-decision decode

#46 | 2014-04-24
US20140114937A1
Physics

Method to shorten hash chains in Lempel-Ziv compression of data with repetitive symbols

#47 | 2014-02-06
US20140040531A1
Physics

Single read based soft-decision decoding of non-volatile memory

InventorID:

644652 ⎘