Dresden
Germany
29
2024-11-07
The entities that hold a legal rights for patent applications filed by inventor Chan Nigel:
Nigel Chan from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
IC STRUCTURE FOR CONNECTED CAPACITANCES AND METHOD OF FORMING SAME
#2 | 2024-08-22SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
#3 | 2023-05-25Semiconductor structure including sectioned well region
#4 | 2022-09-29Eight-transistor static random access memory cell
#5 | 2021-03-18Extended-drain field-effect transistors including a floating gate
#6 | 2020-10-29IC product with a novel bit cell design and a memory array comprising such bit cells
#7 | 2020-03-12Deep fence isolation for logic cells
#8 | 2020-02-27Dual-depth STI cavity extension and method of production thereof
#9 | 2019-10-17High-voltage transistor device with thick gate insulation layers
#10 | 2019-10-10SEMICONDUCTOR DEVICE INCLUDING FDSOI TRANSISTORS WITH COMPACT GROUND CONNECTION VIA BACK GATE
#11 | 2019-08-27Semiconductor devices including self-aligned active regions for planar transistor architecture
#12 | 2019-06-06FinFET SRAM layout and method of making the same
#13 | 2019-02-07Alignment key design rule check for correct placement of abutting cells in an integrated circuit
#14 | 2019-01-31High-voltage transistor device with thick gate insulation layers
#15 | 2019-01-17High voltage transistor using buried insulating layer as gate dielectric
#16 | 2019-01-08SOI-based floating gate memory cell
#17 | 2017-12-19Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof
#18 | 2017-12-14Semiconductor structure with back-gate switching
#19 | 2017-11-30Methods for forming integrated circuits that include a dummy gate structure
#20 | 2017-10-17Integrated circuit including a dummy gate structure and method for the formation thereof
#21 | 2017-09-21Inline monitoring of transistor-to-transistor critical dimension
#22 | 2017-09-12Semiconductor structure with back-gate switching
#23 | 2017-06-20Process monitoring for gate cut mask
#24 | 2017-03-16Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure
#25 | 2016-11-24Device comprising a plurality of FDSOI static random-access memory bitcells and method of operation thereof
#26 | 2014-12-18Device including an array of memory cells and well contact areas, and method for the formation thereof
#27 | 2014-02-20Memory cell assembly including an avoid disturb cell
#28 | 2014-02-20Device comprising a plurality of static random access memory cells and method of operation thereof
#29 | 2012-07-05Hybrid read scheme for multi-level data
656925 ⎘