Austin, Texas
United States
31
2019-11-28
The entities that hold a legal rights for patent applications filed by inventor Riley Mack W.:
Mack W. Riley from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Built-in self-test for receiver channel
#2 | 2015-09-10Circuit design for balanced logic stress
#3 | 2015-09-10Circuit design for balanced logic stress
#4 | 2015-01-27Determining chip burn-in workload using emulated application condition
#5 | 2014-05-29Isolating failing latches using a logic built-in self-test
#6 | 2014-02-20On-chip detection of types of operations tested by an LBIST
#7 | 2014-02-20On-chip detection of types of operations tested by an LBIST
#8 | 2010-04-22Information collection and storage for single core chips to 'N core chips
#9 | 2009-05-14Digital thermal sensor test implementation without using main core voltage supply
#10 | 2009-04-23Controlling asynchronous clock domains to perform synchronous operations
#11 | 2009-04-02Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors
#12 | 2009-03-26Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device
#13 | 2009-02-26Secure power-on reset engine
#14 | 2008-12-25eFuse programming data alignment verification
#15 | 2008-09-18Controlling asynchronous clock domains to perform synchronous operations
#16 | 2008-09-18Using eFuses to store PLL configuration data
#17 | 2008-07-03Multi-use eFuse Macro
#18 | 2008-06-05High speed on-chip serial link apparatus
#19 | 2008-04-03Modifying a test pattern to control power supply noise
#20 | 2008-02-07System and method for reducing test time for loading and executing an architecture verification program for a SoC
#21 | 2007-12-06Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies
#22 | 2007-11-15Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device
#23 | 2007-07-26Method and apparatus for processing error information and injecting errors in a processor system
#24 | 2007-07-19Clock control hierarchy for integrated microprocessors and systems-on-a-chip
#25 | 2007-05-31eFuse programming data alignment verification apparatus and method
#26 | 2007-04-26Validating chip configuration data
#27 | 2007-04-26RUNN counter phase control
#28 | 2007-04-26Method for controlling asynchronous clock domains to perform synchronous operations
#29 | 2007-04-12Apparatus and method for using eFuses to store PLL configuration data
#30 | 2007-04-12System and method for multi-use eFuse macro
#31 | 2007-04-05High speed on-chip serial link apparatus and method
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