Inventor profile of:

Mack W. Riley

City:

Austin, Texas

Country:

United States

Published Applications:

31

Last publication date:

2019-11-28

Top Assignees for applications by Mack W. Riley

The entities that hold a legal rights for patent applications filed by inventor Riley Mack W.:

Recent patent applications by Riley Mack W.

Mack W. Riley from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-11-28
US20190363813A1
Electricity

Built-in self-test for receiver channel

#2 | 2015-09-10
US20150253808A1
Physics

Circuit design for balanced logic stress

#3 | 2015-09-10
US20150253807A1
Physics

Circuit design for balanced logic stress

#4 | 2015-01-27
US14027594
Physics

Determining chip burn-in workload using emulated application condition

#5 | 2014-05-29
US20140149814A1
Physics

Isolating failing latches using a logic built-in self-test

#6 | 2014-02-20
US20140053035A1
Physics

On-chip detection of types of operations tested by an LBIST

#7 | 2014-02-20
US20140053034A1
Physics

On-chip detection of types of operations tested by an LBIST

#8 | 2010-04-22
US20100100357A1
Physics

Information collection and storage for single core chips to 'N core chips

#9 | 2009-05-14
US20090125267A1
Physics

Digital thermal sensor test implementation without using main core voltage supply

#10 | 2009-04-23
US20090106575A1
Physics

Controlling asynchronous clock domains to perform synchronous operations

#11 | 2009-04-02
US20090089636A1
Physics

Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors

#12 | 2009-03-26
US20090083594A1
Physics

Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device

#13 | 2009-02-26
US20090055637A1
Physics

Secure power-on reset engine

#14 | 2008-12-25
US20080320349A1
Physics

eFuse programming data alignment verification

#15 | 2008-09-18
US20080229136A1
Physics

Controlling asynchronous clock domains to perform synchronous operations

#16 | 2008-09-18
US20080225566A1
Electricity

Using eFuses to store PLL configuration data

#17 | 2008-07-03
US20080159010A1
Physics

Multi-use eFuse Macro

#18 | 2008-06-05
US20080133800A1
Physics

High speed on-chip serial link apparatus

#19 | 2008-04-03
US20080082887A1
Physics

Modifying a test pattern to control power supply noise

#20 | 2008-02-07
US20080034261A1
Physics

System and method for reducing test time for loading and executing an architecture verification program for a SoC

#21 | 2007-12-06
US20070283205A1
Physics

Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies

#22 | 2007-11-15
US20070266284A1
Physics

Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device

#23 | 2007-07-26
US20070174679A1
Physics

Method and apparatus for processing error information and injecting errors in a processor system

#24 | 2007-07-19
US20070168688A1
Physics

Clock control hierarchy for integrated microprocessors and systems-on-a-chip

#25 | 2007-05-31
US20070121411A1
Physics

eFuse programming data alignment verification apparatus and method

#26 | 2007-04-26
US20070094420A1
Physics

Validating chip configuration data

#27 | 2007-04-26
US20070092048A1
Electricity

RUNN counter phase control

#28 | 2007-04-26
US20070091933A1
Physics

Method for controlling asynchronous clock domains to perform synchronous operations

#29 | 2007-04-12
US20070081620A1
Electricity

Apparatus and method for using eFuses to store PLL configuration data

#30 | 2007-04-12
US20070081396A1
Physics

System and method for multi-use eFuse macro

#31 | 2007-04-05
US20070079025A1
Physics

High speed on-chip serial link apparatus and method

InventorID:

660946 ⎘