Austin, Texas
United States
31
2023-11-09
The entities that hold a legal rights for patent applications filed by inventor WANG Wei-E:
Wei-E WANG from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS
#2 | 2021-12-02Method of forming multiple-Vt FETS for CMOS circuit applications
#3 | 2021-06-17Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding
#4 | 2021-06-17Method of forming a thermal shield in a monolithic 3-d integrated circuit
#5 | 2020-12-24Method of forming isolation dielectrics for stacked field effect transistors (FETs)
#6 | 2020-12-03Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
#7 | 2020-11-12Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
#8 | 2020-06-25Method of forming a thermal shield in a monolithic 3-D integrated circuit
#9 | 2020-06-18Method of forming multiple-Vt FETs for CMOS circuit applications
#10 | 2020-01-30Metal oxide semiconductor field effect transistor with crystalline oxide layer on a III-V material
#11 | 2019-12-19Method of forming multi-threshold voltage devices and devices so formed
#12 | 2019-05-16Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
#13 | 2019-05-02Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed
#14 | 2019-04-25Method of forming multi-threshold voltage devices and devices so formed
#15 | 2018-05-10Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
#16 | 2018-03-15Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same
#17 | 2018-02-22Method of forming crystalline oxides on III-V materials
#18 | 2018-02-22Horizontal nanosheet FETs and method of manufacturing the same
#19 | 2017-11-23Method of forming internal dielectric spacers for horizontal nanosheet FET architectures
#20 | 2017-09-21Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same
#21 | 2017-05-25Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance
#22 | 2017-04-06Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same
#23 | 2017-02-09Methods of forming nanosheets on lattice mismatched substrates
#24 | 2016-11-03Relaxed semiconductor layers with reduced defects and methods of forming the same
#25 | 2016-10-20Multi-layer fin field effect transistor devices and methods of forming the same
#26 | 2016-03-10RECTANGULAR NANOSHEET FABRICATION
#27 | 2016-02-11Interface layer for gate stack using Opost treatment
#28 | 2015-11-05Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators
#29 | 2015-09-24Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
#30 | 2015-04-02Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods
#31 | 2014-02-27GATED CIRCUIT STRUCTURE WITH ULTRA-THIN, EPITAXIALLY-GROWN TUNNEL AND CHANNEL LAYER
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