Carmichael, California
United States
84
2026-01-08
The entities that hold a legal rights for patent applications filed by inventor Fackenthal Richard E.:
Richard E. Fackenthal from Carmichael, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY DEVICES
#2 | 2025-12-25MEMORY DEVICES
#3 | 2025-11-20Silicon On Insulator Device with Floating Body Effect Mitigation
#4 | 2025-10-09THIN FILM TRANSISTOR RANDOM ACCESS MEMORY
#5 | 2025-07-24MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND CONDUCTIVE SHIELD STRUCTURE
#6 | 2025-07-03SOURCE LINE CONFIGURATIONS FOR A MEMORY DEVICE
#7 | 2025-05-29STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS
#8 | 2025-04-10STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS
#9 | 2024-12-19MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
#10 | 2024-07-25MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND WRAPPED DATA LINE STRUCTURE
#11 | 2024-07-18MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS
#12 | 2024-06-13LOCAL DIGIT LINE (LDL) COUPLING CANCELLATION
#13 | 2024-03-07Thin film transistor random access memory
#14 | 2024-02-29Structures for word line multiplexing in three-dimensional memory arrays
#15 | 2024-02-29Structures for word line multiplexing in three-dimensional memory arrays
#16 | 2023-12-28Memory device having 2-transistor vertical memory cell and separate read and write gates
#17 | 2023-12-07MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES
#18 | 2023-11-30MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES
#19 | 2023-09-21Inverters, and related memory devices and electronic systems
#20 | 2023-09-21Memory device having 2-transistor vertical memory cell and shield structures
#21 | 2023-07-27Memory device having 2-transistor vertical memory cell and wrapped data line structure
#22 | 2023-05-04Memory device having 2-transistor vertical memory cell and conductive shield structure
#23 | 2023-03-28Memory device having 2-transistor vertical memory cell and wrapped data line structure
#24 | 2023-02-02Memory device having 2-transistor vertical memory cell and separate read and write gates
#25 | 2022-11-10Thin film transistor random access memory
#26 | 2022-09-22Erasure decoding for a memory device
#27 | 2022-09-08Thin film transistor random access memory
#28 | 2022-09-08Thin film transistor random access memory
#29 | 2022-09-01Memory device having 2-transistor vertical memory cell and shield structures
#30 | 2022-08-04Enhanced bit flipping scheme
#31 | 2022-05-31Thin film transistor random access memory
#32 | 2022-02-17Source line configuration for a memory device
#33 | 2022-01-20On-demand memory page size
#34 | 2022-01-11Memory cell sensing stress mitigation
#35 | 2021-10-07Erasure decoding for a memory device
#36 | 2021-08-26Wear leveling for random access and ferroelectric memory
#37 | 2021-06-24Source line configuration for a memory device
#38 | 2021-05-13Plate defect mitigation techniques
#39 | 2021-05-06Speculative section selection within a memory device
#40 | 2020-12-31Enhanced bit flipping scheme
#41 | 2020-12-24Speculative section selection within a memory device
#42 | 2020-12-24Efficient power scheme for redundancy
#43 | 2020-11-26Parallel access techniques within memory sections through section independence
#44 | 2020-08-27Source line management for memory cells with floating gates
#45 | 2020-08-13Access schemes for section-based data protection in a memory device
#46 | 2020-06-04Configuration update for a memory device based on a temperature of the memory device
#47 | 2020-05-21Wear leveling
#48 | 2020-02-20Enhanced bit flipping scheme
#49 | 2020-02-20Access schemes for section-based data protection in a memory device
#50 | 2020-01-09Array plate short repair
#51 | 2019-12-26Parallel access techniques within memory sections through section independence
#52 | 2019-12-26Wear leveling for random access and ferroelectric memory
#53 | 2019-11-07On demand memory page size
#54 | 2019-10-31Wear leveling
#55 | 2019-10-01Access schemes for section-based data protection in a memory device
#56 | 2019-09-12Memory systems and memory programming methods
#57 | 2019-02-28Wear leveling for random access and ferroelectric memory
#58 | 2019-02-28On demand memory page size
#59 | 2019-02-07Wear leveling
#60 | 2019-02-07Wear leveling
#61 | 2018-10-04Array plate short repair
#62 | 2018-09-13Plate defect mitigation techniques
#63 | 2018-05-17Parallel access techniques within memory sections through section independence
#64 | 2018-04-12Configuration update for a memory device based on a temperature of the memory device
#65 | 2018-03-29Memory systems and memory programming methods
#66 | 2017-12-21Plate defect mitigation techniques
#67 | 2017-09-14Parallel access techniques within memory sections through section independence
#68 | 2016-09-01Memory systems and memory programming methods
#69 | 2016-01-07Shifting read data
#70 | 2015-09-10Non-volatile memory including reference signal path
#71 | 2015-06-18Memory systems and memory programming methods
#72 | 2015-05-28Rearranging programming data to avoid hard errors
#73 | 2014-08-28Rearranging write data to avoid hard errors
#74 | 2014-03-06Non-volatile memory including reference signal path
#75 | 2012-10-25Adaptive wordline programming bias of a phase change memory
#76 | 2011-12-01Adaptive wordline programming bias of a phase change memory
#77 | 2011-04-07Adaptive wordline programming bias of a phase change memory
#78 | 2009-10-15Multiple layer resistive memory
#79 | 2009-03-19Adaptive wordline programming bias of a phase change memory
#80 | 2009-03-19Interleaved array architecture
#81 | 2008-12-04Biasing a phase change memory device
#82 | 2008-11-27Streaming mode programming in phase change memories
#83 | 2008-09-25Phase change memory with program/verify function
#84 | 2008-09-18Self-referencing redundancy scheme for a content addressable memory
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