Vimercate
Italy
124
2026-06-25
The entities that hold a legal rights for patent applications filed by inventor Fantini Paolo:
Paolo Fantini from Vimercate, IT has applied for patents for these inventions. The list has both pending applications and granted patents:
PILLAR SELECTOR FOR WAFER-ON-WAFER MEMORY
#2 | 2026-05-14MEMORY ARCHITECTURES WITH AMBIPOLAR SEMICONDUCTOR CHANNELS
#3 | 2026-04-23MEMORY DEVICE WITH A THREE-DIMENSIONAL VERTICAL STRUCTURE, AND METHOD FOR DRIVING WORD LINES OF THE MEMORY DEVICE
#4 | 2026-03-05MEMORY CELL FORMATION IN THREE DIMENSIONAL MEMORY ARRAYS USING ATOMIC LAYER DEPOSITION
#5 | 2026-03-05MEMORY APPARATUS AND METHODS FOR ACCESSING AND MANUFACTURING THE SAME
#6 | 2026-02-05MICROELECTRONIC DEVICES, AND RELATED METHODS OF FORMING MICROELECTRONIC DEVICES
#7 | 2026-02-05VERTICAL CHALCOGENIDE MEMORY DEVICE AND METHOD
#8 | 2026-02-05MEMORY DEVICE INCLUDING CAPACITIVE SENSING CIRCUIT
#9 | 2026-02-05MICROELECTRONIC DEVICES AND RELATED MEMORY DEVICES
#10 | 2026-02-05MICROELECTRONIC DEVICES AND RELATED MEMORY DEVICES
#11 | 2026-02-05METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES
#12 | 2025-12-25MEMORY ARCHITECTURES WITH SPLIT PILLARS
#13 | 2025-12-18MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS
#14 | 2025-12-04WORD LINE STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
#15 | 2025-11-20PILLAR AND WORD LINE PLATE ARCHITECTURE FOR A MEMORY ARRAY
#16 | 2025-10-23SPARSE PIERS FOR THREE-DIMENSIONAL MEMORY ARRAYS
#17 | 2025-10-16DENSE PIERS FOR THREE-DIMENSIONAL MEMORY ARRAYS
#18 | 2025-10-02SENSING CIRCUIT IN A VERTICAL MEMORY SYSTEM
#19 | 2025-07-17MEMORY CELLS WITH SIDEWALL AND BULK REGIONS IN VERTICAL STRUCTURES
#20 | 2025-07-17MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
#21 | 2025-04-10MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
#22 | 2025-03-27SPLIT PILLAR ARCHITECTURES FOR MEMORY DEVICES
#23 | 2025-01-30ASYMMETRIC VERTICAL THIN FILM TRANSISTOR SELECTOR
#24 | 2025-01-23MATRIX FORMATION FOR PERFORMING COMPUTATIONAL OPERATIONS IN MEMORY
#25 | 2024-09-19Memory cells with sidewall and bulk regions in vertical structures
#26 | 2024-09-12TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS
#27 | 2024-09-05SIDEWALL STRUCTURES FOR MEMORY CELLS IN VERTICAL STRUCTURES
#28 | 2024-08-29CHALCOGENIDE MEMORY DEVICE COMPOSITIONS
#29 | 2024-07-11METHOD FOR MANUFACTURING A MEMORY DEVICE AND MEMORY DEVICE MANUFACTURED THROUGH THE SAME METHOD
#30 | 2024-06-20DECODING ARCHITECTURE FOR MEMORY DEVICES
#31 | 2024-06-13MEMORY DEVICE WITH LATERALLY FORMED MEMORY CELLS
#32 | 2024-05-16DECODING ARCHITECTURE FOR WORD LINE TILES
#33 | 2024-05-02MEMORY CELLS WITH SIDEWALL AND BULK REGIONS IN PLANAR STRUCTURES
#34 | 2024-03-14Matrix formation for performing computational operations in memory
#35 | 2024-02-29MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS
#36 | 2024-02-15PILLAR AND WORD LINE PLATE ARCHITECTURE FOR A MEMORY ARRAY
#37 | 2024-01-25WORD LINE STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
#38 | 2023-12-07Decoder architectures for three-dimensional memory devices
#39 | 2023-11-02MEMORY CELL FORMATION IN THREE DIMENSIONAL MEMORY ARRAYS USING ATOMIC LAYER DEPOSITION
#40 | 2023-10-19Memory array having air gaps
#41 | 2023-09-28Sparse piers for three-dimensional memory arrays
#42 | 2023-09-28Dense piers for three-dimensional memory arrays
#43 | 2023-09-28Word line structures for three-dimensional memory arrays
#44 | 2023-08-24Chalcogenide memory device compositions
#45 | 2023-08-17Techniques for parallel memory cell access
#46 | 2023-08-03Program current controller and sense circuit for cross-point memory devices
#47 | 2023-07-27Decoding architecture for memory devices
#48 | 2023-06-29Self select memory cell based artificial synapse
#49 | 2023-03-30Vertical 3D memory device and accessing method
#50 | 2023-03-09Decoding architecture for memory tiles
#51 | 2023-02-02Decoding for a memory device
#52 | 2022-12-29Decoding for a memory device
#53 | 2022-12-08Voltage equalization for pillars of a memory array
#54 | 2022-12-01Sidewall structures for memory cells in vertical structures
#55 | 2022-12-01Memory device with laterally formed memory cells
#56 | 2022-12-01Memory cells with sidewall and bulk regions in planar structures
#57 | 2022-12-01Memory cells with sidewall and bulk regions in vertical structures
#58 | 2022-11-17MEMORY APPARATUS AND METHODS FOR ACCESSING AND MANUFACTURING THE SAME
#59 | 2022-10-20Decoding architecture for memory tiles
#60 | 2022-10-20Decoding architecture for memory devices
#61 | 2022-10-20Decoding architecture for word line tiles
#62 | 2022-09-22Memory device and method for manufacturing the same
#63 | 2022-09-22Memory device and method for manufacturing the same
#64 | 2022-09-22LIQUID COMPOSITIONS BASED ON IONIC LIQUIDS FOR THE PROTECTION OF LITHIUM METAL PARTS, ASSOCIATED COATING AND POLYMERIZATION METHODS AND ELECTROCHEMICAL STORAGE SYSTEM
#65 | 2022-06-30Architecture of three-dimensional memory device and methods regarding the same
#66 | 2022-06-16Decoding for a memory device
#67 | 2022-06-16Decoding for a memory device
#68 | 2022-06-09Voltage equalization for pillars of a memory array
#69 | 2022-06-02Split pillar architectures for memory devices
#70 | 2022-04-14Techniques to access a self-selecting memory device
#71 | 2022-03-10Vertical 3D memory device and method for manufacturing the same
#72 | 2022-02-17Method for manufacturing a memory device and memory device manufactured through the same method
#73 | 2021-12-30Three-dimensional memory array
#74 | 2021-07-22Vertical 3D memory device and method for manufacturing the same
#75 | 2021-07-22Memory device with a split pillar architecture
#76 | 2021-02-25Self select memory cell based artificial synapse
#77 | 2021-01-07Split pillar architectures for memory devices
#78 | 2021-01-07Memory device with a split pillar architecture
#79 | 2020-11-05Architecture of three-dimensional memory device and methods regarding the same
#80 | 2020-10-22Transition metal doped germanium-antimony tellurium (GST) memory device components and composition
#81 | 2020-10-15Techniques to access a self-selecting memory device
#82 | 2020-10-08Chalcogenide memory device components and composition
#83 | 2020-09-24Three-dimensional memory array
#84 | 2020-07-16Sub-threshold voltage leakage current tracking
#85 | 2020-06-25Three-dimensional memory array
#86 | 2020-06-04Memory devices and electronic devices including memory materials substantially encapsulated with dielectric materials
#87 | 2020-02-27Transition metal doped germanium-antimony-tellurium (GST) memory device components and composition
#88 | 2020-02-27Systems, methods and devices for programming a multilevel resistive memory cell
#89 | 2020-01-30Chalcogenide memory device components and composition
#90 | 2020-01-30Methods, articles, and devices for pulse adjustments to program a memory cell
#91 | 2019-11-28Techniques to access a self-selecting memory device
#92 | 2019-09-26Sub-threshold voltage leakage current tracking
#93 | 2019-09-17Transition metal doped germanium-antimony-tellurium (GST) memory device components and composition
#94 | 2019-06-20Techniques to access a self-selecting memory device
#95 | 2019-04-18Chalcogenide memory device components and composition
#96 | 2019-04-11Methods, articles, and devices for pulse adjustment to program a memory cell
#97 | 2019-03-21Semiconductor structures including memory materials substantially encapsulated with dielectric materials
#98 | 2019-03-14Chalcogenide memory device components and composition
#99 | 2019-02-07Tip-contact controlled three dimensional (3D) vertical self select memory
#100 | 2018-12-25Chalcogenide memory device components and composition
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