Inventor profile of:

Sagy Levy

City:

Zichron-Yaakov

Country:

Israel

Published Applications:

13

Last publication date:

2020-12-03

Top Assignees for applications by Sagy Levy

The entities that hold a legal rights for patent applications filed by inventor Levy Sagy:

Recent patent applications by Levy Sagy

Sagy Levy from Zichron-Yaakov, IL has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-12-03
US20200381553A1
Electricity

Lateral diffused metal oxide semiconductor field effect (LDMOS) transistor and device having LDMOS transistors

#2 | 2020-09-10
US20200287056A1
Electricity

RADICAL OXIDATION PROCESS FOR FABRICATING A NONVOLATILE CHARGE TRAP MEMORY DEVICE

#3 | 2019-10-17
US20190319104A1
Electricity

NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A DEUTERATED LAYER IN A MULTI-LAYER CHARGE-TRAPPING REGION

#4 | 2018-12-20
US20180366564A1
Electricity

Oxide-nitride-oxide stack having multiple oxynitride layers

#5 | 2018-12-20
US20180366563A1
Electricity

Oxide-nitride-oxide stack having multiple oxynitride layers

#6 | 2017-12-07
US20170352732A1
Electricity

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

#7 | 2017-11-07
US15201460
Electricity

LDMOS device having a low angle sloped oxide

#8 | 2017-01-19
US20170018503A1
Electricity

Semiconductor die with a metal via

#9 | 2016-12-22
US20160372578A1
Electricity

Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure

#10 | 2015-10-01
US20150279969A1
Electricity

Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure

#11 | 2015-08-11
US14475486
Electricity

Double RESURF LDMOS with separately patterned P+ and N+ buried layers formed by shared mask

#12 | 2014-03-13
US20140070315A1
Electricity

Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure

#13 | 2011-03-01
US12005803
-

Trapped-charge non-volatile memory with uniform multilevel programming

InventorID:

683049