Folsom, California
United States
71
2026-06-11
The entities that hold a legal rights for patent applications filed by inventor Ashbaugh Ben J.:
Ben J. Ashbaugh from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:
LOW POWER INFERENCE ENGINE PIPELINE IN A GRAPHICS PROCESSING UNIT
#2 | 2025-10-09Hardware Support for Activation Functions within a Matrix Engine
#3 | 2025-09-18Tensor Memory Accelerator Enhancements
#4 | 2025-08-28PROVIDING NATIVE SUPPORT FOR GENERIC POINTERS IN A GRAPHICS PROCESSING UNIT
#5 | 2025-05-22COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
#6 | 2025-04-24BARRIER STATE SAVE AND RESTORE FOR PREEMPTION IN A GRAPHICS ENVIRONMENT
#7 | 2025-04-10COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS
#8 | 2024-08-01Compute optimization mechanism for deep neural networks
#9 | 2024-08-01CONVOLUTIONAL NEURAL NETWORK OPTIMIZATION MECHANISM
#10 | 2024-07-11NAMED AND CLUSTER BARRIERS
#11 | 2024-07-04SCALABLE AND CONFIGURABLE CLUSTERED SYSTOLIC ARRAY
#12 | 2024-07-04SYNCHRONIZATION FOR DATA MULTICAST IN COMPUTE CORE CLUSTERS
#13 | 2024-07-04DATA MULTICAST IN COMPUTE CORE CLUSTERS
#14 | 2024-05-16INCREASING PROCESSING RESOURCES IN PROCESSING CORES OF A GRAPHICS ENVIRONMENT
#15 | 2024-04-25NAMED AND CLUSTER BARRIERS
#16 | 2024-03-14Implicit fence for write messages
#17 | 2024-02-15CONCURRENT COMPUTE CONTEXT
#18 | 2023-12-14COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS
#19 | 2023-10-05MULTICORE PROCESSOR WITH EACH CORE HAVING INDEPENDENT FLOATING POINT DATAPATH AND INTEGER DATAPATH
#20 | 2023-08-17Compute optimization mechanism for deep neural networks
#21 | 2023-06-22LOW POWER INFERENCE ENGINE PIPELINE IN A GRAPHICS PROCESSING UNIT
#22 | 2023-04-06GRAPHICS PROCESSOR MEMORY ACCESS ARCHITECTURE WITH ADDRESS SORTING
#23 | 2023-03-30Providing native support for generic pointers in a graphics processing unit
#24 | 2023-03-02Compute optimizations for low precision machine learning operations
#25 | 2023-03-02Compute optimizations for low precision machine learning operations
#26 | 2023-01-26PERFORMING GLOBAL MEMORY ATOMICS IN A PRIVATE CACHE OF A SUB-CORE OF A GRAPHICS PROCESSING UNIT
#27 | 2023-01-19Instruction based control of memory attributes
#28 | 2022-12-29Barrier state save and restore for preemption in a graphics environment
#29 | 2022-12-2964-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE
#30 | 2022-12-01Concurrent multi-datatype execution within a processing resource
#31 | 2022-11-17Apparatus, Device, Method, and Computer Program for Scheduling an Execution of Compute Kernels
#32 | 2022-10-20Compute optimization mechanism for deep neural networks
#33 | 2022-08-04Compute optimizations for low precision machine learning operations
#34 | 2022-06-23DATA PARALLEL PROGRAMMING-BASED TRANSPARENT TRANSFER ACROSS HETEROGENEOUS DEVICES
#35 | 2022-06-23DATA PARALLEL PROGRAMMING TASK GRAPH OPTIMIZATION THROUGH DEVICE TELEMETRY
#36 | 2022-06-23INCREMENTAL JUST-IN-TIME (JIT) PERFORMANCE REFINEMENT FOR PROGRAMMABLE LOGIC DEVICE OFFLOAD
#37 | 2022-05-19Compute optimization mechanism for deep neural networks
#38 | 2022-03-17Autonomous vehicle advanced sensing and response
#39 | 2021-12-23Convolutional neural network optimization mechanism
#40 | 2021-11-11Compute optimization mechanism for deep neural networks
#41 | 2021-09-23Extend GPU/CPU coherency to multi-GPU cores
#42 | 2021-09-09NEURAL NETWORK OPTIMIZATION MECHANISM
#43 | 2021-08-19Intelligent thread dispatch and vectorization of atomic operations
#44 | 2021-08-05Compute optimization mechanism for deep neural networks
#45 | 2020-11-19Compute optimizations for low precision machine learning operations
#46 | 2020-09-10System and method to support multiple walkers per command
#47 | 2020-07-02Extend GPU/CPU coherency to multi-GPU cores
#48 | 2020-01-30Compute optimization mechanism for deep neural networks
#49 | 2020-01-16Intelligent thread dispatch and vectorization of atomic operations
#50 | 2019-10-17Autonomous vehicle advanced sensing and response
#51 | 2019-10-03Compute optimizations for low precision machine learning operations
#52 | 2019-08-08Extend GPU/CPU coherency to multi-GPU cores
#53 | 2019-07-04Compute optimizations for low precision machine learning operations
#54 | 2019-06-20Convolutional neural network optimization mechanism
#55 | 2019-05-16Compute unit having independent data paths
#56 | 2018-11-01Compute optimizations for low precision machine learning operations
#57 | 2018-11-01Compute optimizations for low precision machine learning operations
#58 | 2018-11-01Intelligent thread dispatch and vectorization of atomic operations
#59 | 2018-10-25Compute optimization mechanism for deep neural networks
#60 | 2018-10-25Compute optimization mechanism for deep neural networks
#61 | 2018-10-25Compute optimization mechanism for deep neural networks
#62 | 2018-10-25Mixed inference using low and high precision
#63 | 2018-10-25Instructions having support for floating point and integer data types in the same register
#64 | 2018-10-18Autonomous vehicle advanced sensing and response
#65 | 2018-10-18Convolutional neural network optimization mechanism
#66 | 2018-10-18Extend GPU/CPU coherency to multi-GPU cores
#67 | 2017-09-21Facilitating execution-aware hybrid preemption for execution of tasks in computing environments
#68 | 2015-07-02Method and apparatus to facilitate shared pointers in a heterogeneous platform
#69 | 2014-03-13Method and apparatus to facilitate shared pointers in a heterogeneous platform
#70 | 2012-10-04Method and apparatus to facilitate shared pointers in a heterogeneous platform
#71 | 2011-08-25Register allocation with SIMD architecture using write masks
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