JOYDEEP RAY

COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURING INFERENCE

HARDWARE SUPPORT FOR N-DIMENSIONAL MATRIX LOAD AND STORE INSTRUCTIONS

ATOMIC HANDLING FOR DISAGGREGATED 3D STRUCTURED SOCS

DYNAMIC MEMORY RECONFIGURATION

ENGINE TO ENABLE HIGH SPEED CONTEXT SWITCHING VIA ON-DIE STORAGE

BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES

INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION

Hardware Support for Activation Functions within a Matrix Engine

GRAPHICS ENGINE PARTITIONING MECHANISM

DYNAMIC PRECISION FOR NEURAL NETWORK COMPUTE OPERATIONS

EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS

PROVIDING NATIVE SUPPORT FOR GENERIC POINTERS IN A GRAPHICS PROCESSING UNIT

DYNAMIC ROUTING OF TEXTURE LOADS IN GRAPHICS PROCESSING

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

ON CHIP DENSE MEMORY FOR TEMPORAL BUFFERING

GLARE AND OCCLUDED VIEW COMPENSATION FOR AUTOMOTIVE AND OTHER APPLICATIONS

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

DATA INITIALIZATION TECHNIQUES

BARRIER STATE SAVE AND RESTORE FOR PREEMPTION IN A GRAPHICS ENVIRONMENT

EXCEPTION HANDLING FOR DEBUGGING IN A GRAPHICS ENVIRONMENT

COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS

MULTI-TILE MEMORY MANAGEMENT

PROCESSOR POWER MANAGEMENT

PROGRESSIVE MULTISAMPLE ANTI-ALIASING

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

CACHE STRUCTURE AND UTILIZATION

SYSTEMS AND METHODS FOR CACHE OPTIMIZATION

SYSTEMS AND METHODS FOR ERROR DETECTION AND CONTROL FOR EMBEDDED MEMORY AND COMPUTE ELEMENTS

PAGE FAULTING AND SELECTIVE PREEMPTION

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS

SCALAR CORE INTEGRATION

HANDLING PIPELINE SUBMISSIONS ACROSS MANY COMPUTE UNITS

ADAPTIVE MULTISAMPLING BASED ON VERTEX ATTRIBUTES

SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THREAD GROUPS

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

COMPUTE OPTIMIZATION MECHANISM

MULTI-TILE MEMORY MANAGEMENT

Multi-tile memory management

MATRIX OPERATION OPTIMIZATION MECHANISM

CACHE STRUCTURE AND UTILIZATION

GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS

COMPRESSION TECHNIQUES

Efficient data sharing for graphics data processing operations

THREAD SCHEDULING OVER COMPUTE BLOCKS FOR POWER OPTIMIZATION

Graphics system with additional context

Regional Adjustment of Render Rate

INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION

Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration

BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

APPARATUS AND METHOD FOR THROTTLING A RAY TRACING PIPELINE

LOAD STORE CACHE MICROARCHITECTURE

BARRIERS AND SYNCHRONIZATION FOR MACHINE LEARNING AT AUTONOMOUS MACHINES

System, Apparatus And Method For Increasing Performance In A Processor During A Voltage Ramp

Compute optimization mechanism for deep neural networks

CONVOLUTIONAL NEURAL NETWORK OPTIMIZATION MECHANISM

Graphics processor data access and sharing

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

SECTOR CACHE FOR COMPRESSION

BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY

VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES

Fragment compression for coarse pixel shading

LOAD STORE MICROARCHITECTURE CACHE ENHANCEMENTS

DYNAMIC MEMORY RECONFIGURATION

Instructions and logic to perform floating point and integer operations for machine learning

Apparatus and method for managing data bias in a graphics processing architecture

AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD

Architecture for block sparse operations on a systolic array

MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT

INCREASING PROCESSING RESOURCES IN PROCESSING CORES OF A GRAPHICS ENVIRONMENT

BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY

VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES

SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING

Base plus offset addressing for load/store messages

MERGING ATOMICS TO THE SAME CACHE LINE

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION

Implicit fence for write messages

Scheduling of threads for execution utilizing load balancing of thread groups

Regional adjustment of render rate

OFFSET SCALING IN LOAD/STORE MESSAGES

GRAPHICS PROCESSING UNIT PROCESSING AND CACHING IMPROVEMENTS

Compression of machine learning models utilizing pseudo-labeled data training

HARDWARE ENHANCEMENTS FOR MATRIX LOAD/STORE INSTRUCTIONS

MERGING BIT-MASK ATOMICS TO THE SAME DWORD

CONCURRENT COMPUTE CONTEXT

SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES

Scalar core integration

MULTI-RESOLUTION SMOOTHING

COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURING INFERENCE

Efficient data sharing for graphics data processing operations

DYNAMIC PRECISION FOR NEURAL NETWORK COMPUTE OPERATIONS

ENGINE TO ENABLE HIGH SPEED CONTEXT SWITCHING VIA ON-DIE STORAGE

GRAPHICS PROCESSING INTEGRATED CIRCUIT PACKAGE

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

Processor power management