Beaverton, Oregon
United States
59
2025-01-23
The entities that hold a legal rights for patent applications filed by inventor LIN Kevin:
Kevin LIN from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SUBTRACTIVE PLUG AND TAB PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) SPACER-BASED INTERCONNECTS
#2 | 2024-09-12SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS
#3 | 2024-06-27SUBTRACTIVE PLUG AND TAB PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) SPACER-BASED INTERCONNECTS
#4 | 2023-11-02Multi-layer crystalline back gated thin film transistor
#5 | 2022-11-03Subtractively patterned interconnect structures for integrated circuits
#6 | 2022-07-28Grating replication using helmets and topographically-selective deposition
#7 | 2022-05-19Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
#8 | 2022-05-12Integrated circuits and methods for forming thin film crystal layers
#9 | 2022-05-05Subtractively patterned interconnect structures for integrated circuits
#10 | 2022-03-10Integrated circuits with line breaks and line bridges within a single interconnect level
#11 | 2022-02-17Selective metal removal for conductive interconnects in integrated circuitry
#12 | 2021-12-30Multi-layer crystalline back gated thin film transistor
#13 | 2021-11-11Integrated circuits and methods for forming integrated circuits
#14 | 2021-07-22Metal-insulator-metal (MIM) structure supporting high voltage applications and low voltage applications
#15 | 2021-02-18Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects
#16 | 2021-01-07Damascene plug and tab patterning with photobuckets
#17 | 2020-12-31Group III-Nitride devices on SOI substrates having a compliant layer
#18 | 2020-12-10Transistors with metal chalcogenide channel materials
#19 | 2020-11-12Multi-layer crystalline back gated thin film transistor
#20 | 2020-11-05Epitaxial III-N nanoribbon structures for device fabrication
#21 | 2020-10-08Integrated circuits with line breaks and line bridges within a single interconnect level
#22 | 2020-09-24Capacitance reduction for semiconductor devices based on wafer bonding
#23 | 2020-09-03Integrated circuits (IC's) with electro-migration (EM)—resistant segments in an interconnect level
#24 | 2020-08-27Metal-insulator-metal (MIM) structure supporting high voltage applications and low voltage applications
#25 | 2020-07-16Multiple layer metal-insulator-metal (MIM) structure
#26 | 2020-07-02Method to fabricate metal and ferromagnetic metal multilayer interconnect line for skin effect suppression
#27 | 2020-06-18Integrated circuits and methods for forming thin film crystal layers
#28 | 2020-06-18Integrated circuits and methods for forming integrated circuits
#29 | 2020-06-11Adhesion structure for thin film transistor
#30 | 2020-06-11Selective metal removal for conductive interconnects in integrated circuitry
#31 | 2020-02-27COLORED SELF-ALIGNED SUBTRACTIVE PATTERNING
#32 | 2020-01-23Vias and gaps in semiconductor interconnects
#33 | 2020-01-02Self-aligned repeatedly stackable 3D vertical RRAM
#34 | 2020-01-02Inductor and transmission line with air gap
#35 | 2020-01-02Grating replication using helmets and topographically-selective deposition
#36 | 2019-12-26Single-mask, high-q performance metal-insulator-metal capacitor (MIMCAP)
#37 | 2019-12-26Core fill to reduce dishing and metal pillar fill to increase metal density of interconnects
#38 | 2019-12-26Metal and spacer patterning for pitch division with multiple line widths and spaces
#39 | 2019-12-19Pitch quartered three-dimensional air gaps
#40 | 2019-11-21Recessed metal interconnects to mitigate EPE-related via shorting
#41 | 2019-10-24Methods of forming thin film resistor structures utilizing interconnect liner materials
#42 | 2019-09-19Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
#43 | 2019-08-29Resonator structure encapsulation
#44 | 2019-07-11Vias and gaps in semiconductor interconnects
#45 | 2019-07-04Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects
#46 | 2019-05-30Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects
#47 | 2018-07-19Bottom-up selective dielectric cross-linking to prevent via landing shorts
#48 | 2018-06-07Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
#49 | 2018-05-24Doric pillar supported maskless airgap structure for capacitance benefit with unlanded via solution
#50 | 2017-09-14Structure and method to self align via to top and bottom of tight pitch metal interconnect layers
#51 | 2017-09-14Method for creating alternate hardmask cap interconnect structure with increased overlay margin
#52 | 2017-06-08Magnetic nanomechanical devices for stiction compensation
#53 | 2016-11-10Nanowire-based mechanical switching device
#54 | 2016-08-25Method of making an accelerometer
#55 | 2015-08-20Display apparatus including MEMS devices
#56 | 2014-09-18Nanowire-based mechanical switching device
#57 | 2014-06-19Inductive inertial sensor architecture and fabrication in packaging build-up layers
#58 | 2014-03-27Heterogeneous integration of microfluidic devices in package structures
#59 | 2014-03-20Techniques, systems and devices related to acceleration measurement
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