Mark Bohr

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

DEVICE LAYER INTERCONNECTS

DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FOR HIGH PERFORMANCE MICROPROCESSORS

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT

Device layer interconnects

Device, system and method for providing inductor structures

Deep trench via for three-dimensional integrated circuit

Device, method and system for providing a stacked arrangement of integrated circuit dies

COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

Gate contact structure over active gate and method to fabricate same

High density and fine pitch interconnect structures in an electric test apparatus

Device, method and system for providing a stacked arrangement of integrated circuit dies

Package on active silicon semiconductor packages

Substrate-less FinFET diode architectures with backside metal contact and subfin regions

Self-aligned gate edge and local interconnect

Device, system and method for providing inductor structures

Die interconnection scheme for providing a high yielding process for high performance microprocessors

RANDOM-ACCESS MEMORY WITH LOADED CAPACITANCE

Integrated circuit structures having asymmetric source and drain structures

STRUCTURES AND METHODS FOR LARGE INTEGRATED CIRCUIT DIES

High density and fine pitch interconnect structures in an electric test apparatus

Deep trench via for three-dimensional integrated circuit

Device layer interconnects

Self-aligned gate edge and local interconnect

High density and fine pitch interconnect structures in an electric test apparatus

Designs and methods for conductive bumps

Gate contact structure over active gate and method to fabricate same

Self-aligned gate edge and local interconnect and method to fabricate same

COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT

Designs and methods for conductive bumps

Gate contact structure over active gate and method to fabricate same

Self-aligned gate edge and local interconnect and method to fabricate same

COMPOSITE MATERIALS FOR USE IN SEMICONDUCTOR COMPONENTS

COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT

Gate contact structure over active gate and method to fabricate same

Copper-filled trench contact for transistor performance improvement

Selective spacer formation on transistors of different classes on the same device

Silicon interposer-based hybrid voltage regulator system for VLSI devices

Designs and methods for conductive bumps

Forming abrupt source drain metal gate transistors

Selective spacer formation on transistors of different classes on the same device

LOCOS isolation for fully-depleted SOI devices

Copper die bumps with electromigration cap and plated solder

Designs and methods for conductive bumps

Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same

Microcircuit fabrication and interconnection

Forming self-aligned nano-electrodes

Selective spacer formation on transistors of different classes on the same device

Copper-filled trench contact for transistor performance improvement

Strained silicon MOS device with box layer between the source and drain regions

Active region spacer for semiconductor devices and method to form the same

Isolation body for semiconductor devices and method to form the same

Self aligned compact bipolar junction transistor layout and method of making same

Methods of forming electromigration and thermal gradient based fuse structures

Methods of forming electromigration and thermal gradient based fuse structures

Self-aligned contacts to gates

Self-aligned contacts to gates

Self aligned compact bipolar junction transistor layout, and method of making same

Bipolar junction transistor with improved extrinsic base region and method of fabrication

Interconnect shunt used for current distribution and reliability redundancy

Super self-aligned collector device for mono-and hetero bipolar junction transistors and method of making same

Method of forming abrupt source drain metal gate transistors

Transistor performance enhancement using engineered strains

Interconnect shunt used for current distribution and reliability redundancy

Transistors with increased mobility in the channel zone and method of fabrication

Stepped tip junction with spacer layer

Forming self-aligned nano-electrodes

Microcircuit fabrication and interconnection

Microcircuit fabrication and interconnection

Concentration graded carbon doped oxide

Silicon on insulator (SOI) transistor and methods of fabrication

Damascene process for fabricating interconnect layers in an integrated circuit

Bipolar junction transistor with improved extrinsic base region and method of fabrication

Concentration graded carbon doped oxide

Designs and methods for conductive bumps