Austin, Texas
United States
67
2019-04-11
The entities that hold a legal rights for patent applications filed by inventor Gaskins Darius D.:
Darius D. Gaskins from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Domain-differentiated power state coordination system
#2 | 2019-03-28Dynamic reconfiguration of multi-core processor
#3 | 2016-07-21Domain-differentiated power state coordination system
#4 | 2016-07-21Power management synchronization messaging system
#5 | 2016-06-23Method of managing power consumption within a multi-core microprocessor utilizing an inter-core state discovery process to identify a least power-conserving target core state of all of the cores that share the resource
#6 | 2015-03-05Dynamic reconfiguration of multi-core processor
#7 | 2014-11-04Apparatus and method for generating a clock signal with reduced jitter
#8 | 2014-06-19Power state synchronization in a multi-core processor
#9 | 2014-06-12Distributed management of a shared clock source to a multi-core microprocessor
#10 | 2014-03-27Multi-core dies produced by reticle set modification
#11 | 2012-12-27Programmable mechanism for optimizing a synchronous data bus
#12 | 2012-12-27Optimized synchronous data reception mechanism
#13 | 2012-12-27Apparatus and method for delayed synchronous data reception
#14 | 2012-12-27Optimized synchronous strobe transmission mechanism
#15 | 2012-12-27Apparatus and method for advanced synchronous strobe transmission
#16 | 2012-12-27Programmable mechanism for delayed synchronous data reception
#17 | 2012-12-27Programmable mechanism for synchronous strobe advance
#18 | 2012-09-20Multi-core microprocessor internal bypass bus
#19 | 2012-06-28Power state synchronization in a multi-core processor
#20 | 2012-06-28Decentralized power management distributed among multiple processor cores
#21 | 2012-06-28Distributed management of a shared power source to a multi-core microprocessor
#22 | 2012-06-28Master core discovering enabled cores in microprocessor comprising plural multi-core dies
#23 | 2012-06-28Reticle set modification to produce multi-core dies
#24 | 2012-06-14APPARATUS AND METHOD FOR ADAPTIVE BACK BIAS CONTROL OF AN INTEGRATED CIRCUIT
#25 | 2012-06-14APPARATUS AND METHOD FOR SELECTIVE BACK BIAS CONTROL OF AN INTEGRATED CIRCUIT
#26 | 2012-06-14APPARATUS AND METHOD FOR ADJUSTABLE BACK BIAS CONTROL OF AN INTEGRATED CIRCUIT
#27 | 2012-05-08Microprocessor that performs adaptive power throttling
#28 | 2012-02-23Multicore processor power credit management to allow all processing cores to operate at elevated frequency
#29 | 2012-02-23Microprocessor with multicore processor power credit management feature
#30 | 2012-01-05Multicore processor power credit management in which multiple processing cores use shared memory to communicate individual energy consumption
#31 | 2011-08-18Microprocessor with system-robust self-reset capability
#32 | 2011-07-28Multi-core processor with external instruction execution rate heartbeat
#33 | 2011-05-12Avoiding memory access latency by returning hit-modified when holding non-modified data
#34 | 2011-02-10Detection of fuse re-growth in a microprocessor
#35 | 2011-02-10Detection of uncorrectable re-grown fuses in a microprocessor
#36 | 2010-12-23Microprocessor with improved thermal monitoring and protection mechanism
#37 | 2010-10-14Location-based bus termination for multi-core processors
#38 | 2010-10-14Protocol-based bus termination for multi-core processors
#39 | 2010-10-14Configurable bus termination for multi-core/multi-package processor configurations
#40 | 2010-09-09Microprocessor that performs adaptive power throttling
#41 | 2010-08-03Location-based bus termination for multi-core/multi-package processor configurations
#42 | 2010-03-25Microprocessor with selective substrate biasing for clock-gated functional blocks
#43 | 2010-03-25Microprocessor with substrate bias clamps
#44 | 2008-07-31Encoded mechanism for source synchronous strobe lockout
#45 | 2008-02-14Microprocessor with improved thermal monitoring and protection mechanism
#46 | 2007-11-01Microprocessor capable of dynamically increasing its performance in response to varying operating temperature
#47 | 2007-10-25Microprocessor with improved performance during P-state transitions
#48 | 2007-10-25Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature
#49 | 2007-10-02Mechanism for providing measured power management transitions in a microprocessor
#50 | 2007-05-24Apparatus and method for dynamic configuration of temperature profile in an integrated circuit
#51 | 2007-04-19Apparatus and method for enabling a multi-processor environment on a bus
#52 | 2007-04-05Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test
#53 | 2007-02-08Data bus mechanism for dynamic source synchronized sampling adjust
#54 | 2007-02-01Apparatus and method for writing a sparsely populated cache line to memory
#55 | 2007-01-25DATA BUS LOGICAL BYPASS MECHANISM
#56 | 2007-01-25Apparatus and method for ordering transaction beats in a data transfer
#57 | 2007-01-11Flexible width data protocol
#58 | 2007-01-11Apparatus and method for quad-pumped address bus
#59 | 2007-01-11Microprocessor apparatus and method for enabling variable width data transfers
#60 | 2007-01-11Target readiness protocol for contiguous write
#61 | 2007-01-11Apparatus and method for dynamic configuration of temperature profile in an integrated circuit
#62 | 2005-09-29Sense mechanism for microprocessor bus inversion
#63 | 2005-08-18Instantaneous frequency-based microprocessor power management
#64 | 2005-08-18Method and apparatus for microprocessor temperature control
#65 | 2005-06-23Frequency-voltage mechanism for microprocessor power management
#66 | 2005-06-07Integrated circuit timing debug apparatus and method
#67 | 2005-02-24Resource utilization mechanism for microprocessor power management
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