Santa Clara, California
United States
64
2026-05-07
The entities that hold a legal rights for patent applications filed by inventor Gottschlich Justin E.:
Justin E. Gottschlich from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:
COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURING INFERENCE
#2 | 2025-05-22COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
#3 | 2025-02-20PROGRAMMABLE COARSE GRAINED AND SPARSE MATRIX COMPUTE HARDWARE WITH ADVANCED SCHEDULING
#4 | 2024-08-01Compute optimization mechanism for deep neural networks
#5 | 2024-03-14NEURAL NETWORK SCHEDULING MECHANISM
#6 | 2024-01-11COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURING INFERENCE
#7 | 2023-12-07Programmable coarse grained and sparse matrix compute hardware with advanced scheduling
#8 | 2023-10-19DYNAMIC DISTRIBUTED TRAINING OF MACHINE LEARNING MODELS
#9 | 2023-08-17Compute optimization mechanism for deep neural networks
#10 | 2023-02-09AUTONOMOUS VEHICLE NEURAL NETWORK OPTIMIZATION
#11 | 2023-01-12METHODS AND APPARATUS TO GENERATE ANOMALY DETECTION DATASETS
#12 | 2022-11-17Coordination and increased utilization of graphics processors during inference
#13 | 2022-10-20Compute optimization mechanism for deep neural networks
#14 | 2022-10-13Neural network scheduling mechanism
#15 | 2022-05-26Programmable coarse grained and sparse matrix compute hardware with advanced scheduling
#16 | 2022-05-19Compute optimization mechanism for deep neural networks
#17 | 2022-03-17Autonomous vehicle advanced sensing and response
#18 | 2021-12-16Efficient sharing and compression expansion of data across processing systems
#19 | 2021-11-11Compute optimization mechanism for deep neural networks
#20 | 2021-09-23Extend GPU/CPU coherency to multi-GPU cores
#21 | 2021-09-09NEURAL NETWORK OPTIMIZATION MECHANISM
#22 | 2021-08-05Compute optimization mechanism for deep neural networks
#23 | 2021-07-01Coordination and increased utilization of graphics processors during inference
#24 | 2021-02-04Programmable coarse grained and sparse matrix compute hardware with advanced scheduling
#25 | 2020-12-17Neural network scheduling mechanism
#26 | 2020-07-02Extend GPU/CPU coherency to multi-GPU cores
#27 | 2020-06-25Efficient sharing and compression expansion of data across processing systems
#28 | 2020-01-30Compute optimization mechanism for deep neural networks
#29 | 2020-01-16Smart autonomous machines utilizing cloud, error corrections, and predictions
#30 | 2019-10-17Autonomous vehicle advanced sensing and response
#31 | 2019-09-26Coordination and increased utilization of graphics processors during inference
#32 | 2019-08-08Extend GPU/CPU coherency to multi-GPU cores
#33 | 2019-05-09Programmable coarse grained and sparse matrix compute hardware with advanced scheduling
#34 | 2018-11-15Methods and apparatus to generate anomaly detection datasets
#35 | 2018-11-01Programmable coarse grained and sparse matrix compute hardware with advanced scheduling
#36 | 2018-11-01Autonomous machines through cloud, error corrections, and predictions
#37 | 2018-11-01Storage management for machine learning at autonomous machines
#38 | 2018-10-25Compute optimization mechanism for deep neural networks
#39 | 2018-10-25Compute optimization mechanism for deep neural networks
#40 | 2018-10-25Efficient sharing and compression expansion of data across processing systems
#41 | 2018-10-25Coordination and increased utilization of graphics processors during inference
#42 | 2018-10-25Compute optimization mechanism for deep neural networks
#43 | 2018-10-25Dynamic distributed training of machine learning models
#44 | 2018-10-25Neural network optimization mechanism
#45 | 2018-10-25Neural network training mechanism
#46 | 2018-10-18Autonomous vehicle advanced sensing and response
#47 | 2018-10-18Extend GPU/CPU coherency to multi-GPU cores
#48 | 2018-10-18AUTONOMOUS VEHICLE NEURAL NETWORK OPTIMIZATION
#49 | 2018-10-11Neural network scheduling mechanism
#50 | 2018-06-21Dynamic runtime task management
#51 | 2016-12-22Transactional memory management techniques
#52 | 2016-10-13Methods and systems for performing a replay execution
#53 | 2016-09-29Technologies for root cause identification of use-after-free memory corruption bugs
#54 | 2016-08-11Techniques for detecting race conditions
#55 | 2016-06-23Apparatus and method for a profiler for hardware transactional memory programs
#56 | 2015-10-01Software replayer for transactional memory programs
#57 | 2015-10-01Enabling maximum concurrency in a hybrid transactional memory system
#58 | 2015-07-02Processor with transactional capability and logging circuitry to report transactional operations
#59 | 2015-06-18Unbounded transactional memory with forward progress guarantees using a hardware global lock
#60 | 2015-04-09Transactional memory management techniques
#61 | 2015-03-12Apparatus and method for improved lock elision techniques
#62 | 2014-12-11VISUALIZING RECORDED EXECUTIONS OF MULTI-THREADED SOFTWARE PROGRAMS FOR PERFORMANCE AND CORRECTNESS
#63 | 2014-09-18Shared memory interleavings for instruction atomicity violations
#64 | 2014-03-27Replay execution of instructions in thread chunks in the chunk order recorded during previous execution
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