Folsom, California
United States
76
2026-02-05
The entities that hold a legal rights for patent applications filed by inventor Navale Aditya:
Aditya Navale from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:
POST-SYNCHRONIZATION OPERATIONS IN MULTI-TILE PROCESSOR COMPUTING
#2 | 2025-08-21ALLOCATION AND SYNCHRONIZATION OF MULTIPLE QUEUES BY A GRAPHICS PROCESSING UNIT
#3 | 2025-07-17GRAPHICS PROCESSOR MID-THREAD PREEMPTION
#4 | 2025-07-17BINDLESS THREAD DISPATCH MID-THREAD PREEMPTION ON A GRAPHICS PROCESSOR
#5 | 2024-06-06Tile sequencing mechanism
#6 | 2024-02-15CONCURRENT COMPUTE CONTEXT
#7 | 2024-02-08Apparatus and Method for Concurrent Performance Monitoring per Compute Hardware Context
#8 | 2023-09-28COMPRESSION USING A FLAT MAPPING IN VIRTUAL ADDRESS SPACE
#9 | 2023-09-21LOCAL MEMORY TRANSLATION TABLE ACCESSED AND DIRTY FLAGS
#10 | 2023-09-21LOCAL MEMORY TRANSLATION TABLE
#11 | 2023-09-21MULTI-RENDER PARTITIONING
#12 | 2023-09-21FLEXIBLE PARTITIONING OF GPU RESOURCES
#13 | 2023-09-21HARD PARTITIONING VIA INTRA-SOC COMPOSITION
#14 | 2023-09-14PAGING SUPPORT FOR ENCRYPTED GPU BUFFERS
#15 | 2023-06-29UNIFIED STATELESS COMPRESSION SYSTEM FOR UNIVERSALLY CONSUMABLE COMPRESSION
#16 | 2023-04-13MODULAR GPU ARCHITECTURE FOR CLIENTS AND SERVERS
#17 | 2023-04-06GRAPHICS PROCESSOR MEMORY ACCESS ARCHITECTURE WITH ADDRESS SORTING
#18 | 2023-03-30UNIFIED SUBMIT PORT FOR GRAPHICS PROCESSING
#19 | 2023-02-09WORKLOAD SCHEDULING AND DISTRIBUTION ON A DISTRIBUTED GRAPHICS DEVICE
#20 | 2022-12-15Apparatus and method for scalable error detection and reporting
#21 | 2022-08-18Tile sequencing mechanism
#22 | 2022-05-05COMPUTE OPTIMIZATION IN GRAPHICS PROCESSING
#23 | 2022-05-05GRAPHICS SECURITY WITH SYNERGISTIC ENCRYPTION, CONTENT-BASED AND RESOURCE MANAGEMENT TECHNOLOGY
#24 | 2022-03-29Range based flushing mechanism
#25 | 2022-03-10Interconnected systems fence mechanism
#26 | 2021-12-30Tile sequencing mechanism
#27 | 2021-11-11COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS
#28 | 2021-09-09Systems and methods in a graphics environment for providing shared virtual memory addressing support for a host system
#29 | 2021-09-02Apparatus and method for scalable error detection and reporting
#30 | 2021-08-19Asynchronous execution mechanism
#31 | 2021-08-05Workload scheduling and distribution on a distributed graphics device
#32 | 2020-12-24Asynchronous execution mechanism
#33 | 2020-10-29Memory mapped virtual doorbell mechanism
#34 | 2020-07-09Workload scheduling and distribution on a distributed graphics device
#35 | 2020-05-28Apparatus and method for scalable error detection and reporting
#36 | 2020-03-12System and method for content protection in a graphics or video subsystem
#37 | 2020-02-06Single input multiple data processing mechanism
#38 | 2020-01-02Method and apparatus for simultaneously executing multiple contexts on a graphics engine
#39 | 2019-10-03System, apparatus and method for multi-die distributed memory mapped input/output support
#40 | 2019-07-25Method and apparatus for a scalable interrupt infrastructure
#41 | 2019-04-04Tile aware sector cache for graphics
#42 | 2018-08-02Efficient fine grained processing of graphics workloads in a virtualized environment
#43 | 2018-06-21Single input multiple data processing mechanism
#44 | 2017-12-14Hardware assist for privilege access violation checks
#45 | 2017-11-30Hierarchical lossless compression and null data support
#46 | 2017-06-15Scalable geometry processing within a checkerboard multi-GPU configuration
#47 | 2017-01-05Memory mapping for a graphics processing unit
#48 | 2016-08-18Apparatus and method for scheduling graphics processing unit workloads from virtual machines
#49 | 2016-06-30Ordering mechanism for offload graphics scheduling
#50 | 2016-05-26Memory address re-mapping of graphics data
#51 | 2016-01-28Mid-thread pre-emption with software assisted context switch
#52 | 2015-12-31Efficient hardware mechanism to ensure shared resource data coherency across draw calls
#53 | 2015-12-03Method and apparatus for parallel pixel shading
#54 | 2015-10-08Process synchronization between engines using data in a memory location
#55 | 2015-10-01System coherency in a distributed graphics processor hierarchy
#56 | 2015-10-01Priority based context preemption
#57 | 2015-09-24Dynamic cache and memory allocation for memory subsystems
#58 | 2015-05-07Method and apparatus for supporting programmable software context state execution during hardware context restore flow
#59 | 2015-04-16Supporting atomic operations as post-synchronization operations in graphics processing architectures
#60 | 2015-01-01Mid command buffer preemption for graphics workloads
#61 | 2014-12-25Page management approach to fully utilize hardware caches for tiled rendering
#62 | 2014-10-16Scalable geometry processing within a checkerboard multi-GPU configuration
#63 | 2014-09-18Memory mapping for a graphics processing unit
#64 | 2014-06-12Memory based semaphores
#65 | 2014-04-17Hardware assist for privilege access violation checks
#66 | 2014-03-06Direct ring 3 submission of processing jobs to adjunct processors
#67 | 2014-01-23CPU independent graphics scheduler for performing scheduling operations for graphics hardware
#68 | 2014-01-23Fast mechanism for accessing 2nĀ±1 interleaved memory system
#69 | 2013-11-07Memory address re-mapping of graphics data
#70 | 2013-06-20Dynamic error handling using parity and redundant rows
#71 | 2013-01-31Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
#72 | 2012-06-07Memory address re-mapping of graphics data
#73 | 2011-02-17Memory address re-mapping of graphics data
#74 | 2010-12-30Creating secure communication channels between processing elements
#75 | 2009-07-02Boosting graphics performance based on executing workload
#76 | 2008-01-03Apparatus and method for memory address re-mapping of graphics data
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