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Inventor profile of:

David Mark

City:

San Jose, California

Country:

United States

Published Applications:

8

Last publication date:

2011-08-16

Top Assignees for applications by David Mark

The entities that hold a legal rights for patent applications filed by inventor Mark David:

  • XILINX, INC. 8 San Jose, CA United States

Recent patent applications by Mark David

David Mark from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-08-16
US11732859
-

Method of metal pattern inspection verification

#2 | 2008-11-18
US11588771
-

Method of and system for monitoring the functionality of a wafer probe site

#3 | 2008-04-22
US11064129
-

Circuit for and method of determining the location of a defect in an integrated circuit

#4 | 2007-08-28
US10619136
-

Method for gross I/O functional test at wafer sort

#5 | 2007-06-05
US11016473
-

Test circuit for and method of identifying a defect in an integrated circuit

#6 | 2006-12-05
US10703326
-

Method and circuits for localizing defective interconnect resources in programmable logic devices

#7 | 2006-10-17
US10683919
-

Methods of testing interconnect lines in programmable logic devices using partial reconfiguration

#8 | 2005-05-03
US10280611
-

Method and apparatus for localizing faults within a programmable logic device

InventorID:

7252277 ⎘

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