Mark A. Anders

ENERGY-EFFICIENT PRE-ENCODED BOOTH FOR STATIONARY WEIGHTS AND ACTIVATIONS

HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

MEMORY TIMING CHARACTERIZATION CIRCUITRY

HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE

PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

High bandwidth core to network-on-chip interface

FLOATING POINT MULTIPLY-ACCUMULATE UNIT FOR DEEP LEARNING

Instructions and logic to perform floating point and integer operations for machine learning

AREA AND ENERGY EFFICIENT MULTI-PRECISION MULTIPLY-ACCUMULATE UNIT-BASED PROCESSOR

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

VARIABLE FORMAT, VARIABLE SPARSITY MATRIX MULTIPLICATION INSTRUCTION

Instructions and logic to perform floating-point and integer operations for machine learning

Variable format, variable sparsity matrix multiplication instruction

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Simon-based hashing for fuse validation

Systems, apparatuses, and methods for K nearest neighbor search

Scalable crossbar apparatus and method for arranging crossbar circuits

Systems, apparatuses, and methods for K nearest neighbor search

Adaptively switched network-on-chip

Spatially divided circuit-switched channels for a network-on-chip

Combined guaranteed throughput and best effort network-on-chip

Parallel direction decode circuits for network-on-chip

Link delay based routing apparatus for a network-on-chip

Pipelined hybrid packet/circuit-switched network-on-chip

System for multicast and reduction communications on a network-on-chip

High bandwidth core to network-on-chip interface

Pointer chasing across distributed memory

Edge-aware synchronization of a data signal

Instruction and logic for a simon block cipher

Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)

Architecture and method for hybrid circuit-switched and packet-switched router

Variable precision floating point multiply-add circuit

Motion estimation for video processing

Reconfigurable SIMD vector processing system

Distributed ring control circuits for Viterbi traceback

Viterbi traceback

Sparse tree adder circuit

Data converter and a delay threshold comparator

Voltage-level converter

Transition-encoder sense amplifier

Distributed ring control circuits for Viterbi traceback

Apparatus and method for an address generation circuit

Single ended current-sensed bus with novel static power free receiver circuit

Low loss interconnect structure for use in microelectronic circuits

Low-swing bus driver and receiver

Encoder and decoder circuits for dynamic bus

Low loss interconnect structure for use in microelectronic circuits

Adder circuit with sense-amplifier multiplexer front-end