Gregory A. Overkamp

Multi-cycle instructions

Efficient emulation instruction dispatch based on instruction width

FIFO write/LIFO read trace buffer with software and hardware loop compression

Decode and dispatch of multi-issue and multiple width instructions

Hardware loops and pipeline system using advanced generation of loop parameters

Valid bit generation and tracking in a pipelined processor

Processor stalling

Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destination

Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor

Hardware loops

Method and apparatus for restoring registers after cancelling a multi-cycle instruction

Event handling