Patrick Morrow

DEVICE STACKING IN INTEGRATED CIRCUIT LAYERS USING HIGH ACCURACY BONDING

RESONANT CLOCKING ARCHITECTURE

BALANCED STATIC RANDOM-ACCESS MEMORY (SRAM)

STATIC RANDOM-ACCESS MEMORY

INTEGRATED CIRCUIT STRUCTURES WITH SUB-FIN ISOLATION

BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES OF DEVICES

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING REMOVED SUBSTRATE

INTEGRATED CIRCUIT STRUCTURES HAVING STACKED TRANSISTORS WITH BACKSIDE ACCESS

MICROELECTRONIC ASSEMBLIES

TRANSISTOR WITH CHANNEL-SYMMETRIC GATE

WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS

INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE CONTACT STITCHING

STACKED TRANSISTORS

INTEGRATED CIRCUIT STRUCTURES WITH SUB-FIN ISOLATION

TRANSISTOR WITH CHANNEL-SYMMETRIC GATE

N-P BALANCED MULTI-PORT REGISTER FILE WITH COMPLEMENTARY FIELD-EFFECT TRANSISTORS (CFETS)

VERTICALLY SPACED INTRA-LEVEL INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT DEVICES

STACKED FORKSHEET TRANSISTORS

SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS

High Density Transistor and Routing Track Architecture

INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TESTING

INTEGRATED CIRCUIT STRUCTURES WITH CAVITY SPACERS

BACKSIDE CONTACTED SUB-FIN DIODES

Sideways vias in isolation areas to contact interior layers in stacked devices

THREE-TRANSISTOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY GAIN CELL IN COMPLEMENTARY FIELD EFFECT TRANSISTOR PROCESS

Backside contact structures and fabrication for metal on both sides of devices

Stacked source-drain-gate connection and process for forming such

INTEGRATED CIRCUIT CONTACT STRUCTURES

INTEGRATED CIRCUIT (IC) DEVICE WITH METAL LAYER INCLUDING STAGGERED METAL LINES

PACKAGE ARCHITECTURE FOR QUASI-MONOLITHIC CHIP WITH BACKSIDE POWER

MULTI-PORTED REGISTER FILE WITH CFETS

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP OXIDATION APPROACH

DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS

SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS

LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES

SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURCE AND DRAIN

DUAL METAL SILICIDE FOR STACKED TRANSISTOR DEVICES

3D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND NMOS

3D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS

Forming an oxide volume within a fin

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING MULTIPLE BOTTOM-UP OXIDATION APPROACHES

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

SRAM WITH P-TYPE ACCESS TRANSISTORS AND COMPLEMENTARY FIELD-EFFECT TRANSISTOR TECHNOLOGY

Backside contact structures and fabrication for metal on both sides of devices

Stacked source-drain-gate connection and process for forming such

WRAP-AROUND CONTACTS FOR STACKED TRANSISTORS

NON-REACTIVE EPI CONTACT FOR STACKED TRANSISTORS

SOURCE OR DRAIN METALLIZATION PRIOR TO CONTACT FORMATION IN STACKED TRANSISTORS

FRONTSIDE AND BACKSIDE EPI CONTACT

BACKSIDE SHUNT CONTACT FOR IMPROVED INTEGRATED CIRCUIT LAYOUT

ASYMMETRIC GATE STRUCTURES AND CONTACTS FOR STACKED TRANSISTORS

Stacked trigate transistors with dielectric isolation and process for forming such

Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures

VERTICAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES

LATERAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES

LATERAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES

GATE-TO-GATE ISOLATION FOR STACKED TRANSISTOR ARCHITECTURE VIA SELECTIVE DIELECTRIC DEPOSITION STRUCTURE

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

SUBSTRATE-LESS DIODE, BIPOLAR AND FEEDTHROUGH INTEGRATED CIRCUIT STRUCTURES

Metallization structures for stacked device connectivity and their methods of fabrication

Vertically stacked finFETs and shared gate patterning

Non-silicon N-type and P-type stacked transistors for integrated circuit devices

Microelectronic assemblies

Microelectronic assemblies

TRANSISTOR CELLS INCLUDING A DEEP VIA LINED WITH A DIELECTRIC MATERIAL

Wrap-around source/drain method of making contacts for backside metals

Wrap-around source/drain method of making contacts for backside metals

Fabrication and use of through silicon vias on double sided interconnect device

Stacked transistors

Isolation walls for vertically stacked transistor structures

Forksheet transistor architectures

Vertically stacked transistor devices with isolation wall structures containing an electrical conductor

Backside contact structures and fabrication for metal on both sides of devices

Vias in composite IC chip structures

Integrated circuit device with crenellated metal trace layout

Stacked forksheet transistors

Vertically spaced intra-level interconnect line metallization for integrated circuit devices

Composite IC chips including a chiplet embedded within metallization layers of a host IC chip

Vertically stacked transistors in a fin

Metallization structures under a semiconductor device layer

Stacked transistor structures with asymmetrical terminal interconnects

Forksheet transistor architectures

Apparatus with multi-wafer based device and method for forming such

Gate-all-around integrated circuit structures having removed substrate

PN-body-tied field effect transistors

Integrated circuit device structures and double-sided electrical testing

Multi-level spin logic

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Techniques for revealing a backside of an integrated circuit device, and associated configurations

Packaged device with a chiplet comprising memory resources

Composite IC chips including a chiplet embedded within metallization layers of a host IC chip

Vias in composite IC chip structures

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

Backside source/drain replacement for semiconductor devices with metallization on both sides

Bottom fin trim isolation aligned with top gate for stacked device architectures

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Device including air gapping of gate spacers and other dielectrics and process for providing such

Stacked source-drain-gate connection and process for forming such

DEVICES WITH AIR GAPPING BETWEEN STACKED TRANSISTORS AND PROCESS FOR PROVIDING SUCH