Frank Hellwig

HIERARCHICALLY CONFIGURED INTERCONNECT-BASED ACCESS MECHANISM

CONSOLIDATION OF INTERRUPT LOST EVENTS IN MULTI-LEVEL INTERRUPT SYSTEM

PROCESSING OF INTERRUPTS

Direct memory access circuit, microcontroller, and method of controlling a direct memory access

Write busy signaling for interface structures

Systems, devices, and methods for dynamic allocation

Interconnection of protected information between components

Master, slave, master-slave-communication system, on-chip interconnect system, method for operating a master, method for operating a slave, method for operating a master-slave communication system and method for operating an on-chip interconnect system

Security device with extended reliability

DISTRIBUTION OF INTERCONNECT BANDWIDTH AMONG MASTER AGENTS

SERVICE REQUEST INTERRUPT ROUTER FOR VIRTUAL INTERRUPT SERVICE PROVIDERS

Data processing device and method for processing an interrupt

Resource protection

CONTROL DEVICE AND METHOD FOR SECURING DATA

Service request interrupt router for virtual interrupt service providers

Security device with extended reliability

Virtual machine monitor interrupt support for computer processing unit (CPU)

Scalable multi-core system-on-chip architecture on multiple dice for high end microcontroller

Memory protecting unit and method for protecting a memory address space

Scalable multi-core system-on-chip architecture on multiple dice for high end microcontroller

Control device including direct memory access controller for securing data and method thereof

Service request interrupt router with shared arbitration unit

Bus system and method of protected memory access

Conditional links for direct memory access controllers

DMA integrity checker

Systems and methods for secure interrupt handling