Barry L. Minor

System and method for photorealistic imaging workload distribution

Method to reduce queue synchronization of multiple work items in a system with high memory latency between processing nodes

Reducing cross queue synchronization on systems with low memory latency across distributed processing nodes

Method to dynamically distribute a multi-dimensional work set across a multi-core system

Security screening image analysis simplification through object pattern identification

Efficient communication of producer/consumer buffer status

System and method for iterative interactive ray tracing in a multiprocessor environment

Method for managing hardware resources within a simultaneous multi-threaded processing system

Reducing queue synchronization of multiple work items in a system with high memory latency between processing nodes

System for reducing data transfer latency to a global queue by generating bit mask to identify selected processing nodes/units in multi-node data processing system

Portioning and routing of work in a multiple processor system

Dynamically distribute a multi-dimensional work set across a multi-core system

Method for managing hardware resources within a simultaneous multi-threaded processing system

Process integrity of work items in a multiple processor system

Customizing function behavior based on cache and scheduling parameters of a memory argument

Efficient multi-level software cache using SIMD vector permute functionality

Security screening image analysis simplification through object pattern identification

System and method for photorealistic imaging workload distribution

System and method for photorealistic imaging using ambient occlusion

System for iterative interactive ray tracing in a multiprocessor environment

System and method for a software managed cache in a multiprocessing environment

Partitioning processor resources based on memory usage

Efficient communication of producer/consumer buffer status

Ray tracing with depth buffered display

Balancing computational load across a plurality of processors

Dynamically partitioning processing across a plurality of heterogeneous processors

System and method for efficient implementation of software-managed cache

Virtual devices using a plurality of processors

Managing position independent code using a software framework

Hiding memory latency

Task Queue Management of Virtual Devices Using a Plurality of Processors

Adaptive span computation during ray casting

System and product for DMA controller with multi-dimensional line-walking functionality

System and method for cache optimized data formatting

Memory compression method and apparatus for heterogeneous processor architectures in an information handling system

EFFICIENT TRIANGULAR SHAPED MESHES

Apparatus and method for efficient communication of producer/consumer buffer status

Efficient triangular shaped meshes

Destructive DMA lists

Input device for providing position information to information handling systems

Adaptive span computation when ray casting

Ray tracing with depth buffered display

Managing position independent code using a software framework

Partitioning processor resources based on memory usage

System and method for hiding memory latency

System and method for DMA controller with multi-dimensional line-walking functionality

System and method for cache optimized data formatting

System and method for terrain rendering using a limited memory footprint

System and method for blending data sampling techniques

Efficient function interpolation using SIMD vector permute functionality

Task queue management of virtual devices using a plurality of processors

Balancing computational load across a plurality of processors

Dynamically partitioning processing across plurality of heterogeneous processors

System and method for compiling source code for multi-processor environments

Virtual devices using a pluarlity of processors