Murphy, Texas
United States
41
2026-06-11
The entities that hold a legal rights for patent applications filed by inventor Pierson Matthew D.:
Matthew D. Pierson from Murphy, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS
#2 | 2025-02-06BUS ARCHITECTURE WITH TRANSACTION CREDIT SYSTEM
#3 | 2024-12-12PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
#4 | 2023-12-28Slot/sub-slot prefetch architecture for multiple memory requestors
#5 | 2023-02-16SECURE MASTER AND SECURE GUEST ENDPOINT SECURITY FIREWALL
#6 | 2022-08-18Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels
#7 | 2021-11-11Slot/sub-slot prefetch architecture for multiple memory requestors
#8 | 2021-08-05Highly integrated scalable, flexible DSP megamodule architecture
#9 | 2021-01-14Multicore bus architecture with non-blocking high performance transaction credit system
#10 | 2020-02-20Slot/sub-slot prefetch architecture for multiple memory requestors
#11 | 2019-11-21Multicore bus architecture with non-blocking high performance transaction credit system
#12 | 2019-05-16Highly integrated scalable, flexible DSP megamodule architecture
#13 | 2018-12-13Secure master and secure guest endpoint security firewall
#14 | 2018-10-11Multicore bus architecture with non-blocking high performance transaction credit system
#15 | 2018-08-23Slot/sub-slot prefetch architecture for multiple memory requestors
#16 | 2017-06-01Highly integrated scalable, flexible DSP megamodule architecture
#17 | 2016-06-09Multicore, multibank, fully concurrent coherence controller
#18 | 2016-05-05Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels
#19 | 2016-05-05Multicore bus architecture with non-blocking high performance transaction credit system
#20 | 2016-03-03Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
#21 | 2016-02-25Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
#22 | 2015-12-24Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
#23 | 2015-01-15Highly integrated scalable, flexible DSP megamodule architecture
#24 | 2014-06-05Multicore, multibank, fully concurrent coherence controller
#25 | 2014-05-29Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
#26 | 2014-05-22Secure master and secure guest endpoint security firewall
#27 | 2014-05-22Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
#28 | 2014-04-24Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
#29 | 2014-04-24Distributed data return buffer for coherence system with speculative address support
#30 | 2014-04-24Deadlock-avoiding coherent system on chip interconnect
#31 | 2014-04-24Coherence controller slot architecture allowing zero latency write commit
#32 | 2014-04-24Multi processor bridge with mixed Endian mode support
#33 | 2014-04-24Hazard detection and elimination for coherent endpoint allowing out-of-order execution
#34 | 2014-04-24Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
#35 | 2014-04-24Optimum cache access scheme for multi endpoint atomic access in a multicore system
#36 | 2014-04-24Multi processor multi domain conversion bridge with out of order return buffering
#37 | 2012-03-22Prefetcher with arbitrary downstream prefetch cancelation
#38 | 2012-03-22Double-buffered data storage to reduce prefetch generation stalls
#39 | 2012-03-22Prefetch address hit prediction to reduce memory access latency
#40 | 2012-03-22Prefetch stream filter with FIFO allocation and stream direction prediction
#41 | 2012-03-22Slot/sub-slot prefetch architecture for multiple memory requestors
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