Niloy Mukherjee

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Metal filament memory cells

RESISTIVE RANDOM ACCESS MEMORY CELL

Asymmetric selectors for memory cells

CONDUCTIVE BRIDGE RESISTIVE RANDOM ACCESS MEMORY CELL

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Techniques for forming contacts to quantum well transistors

Strained channel region transistors employing source and drain stressors and systems including the same

TECHNIQUES FOR FILAMENT LOCALIZATION, EDGE EFFECT REDUCTION, AND FORMING/SWITCHING VOLTAGE REDUCTION IN RRAM DEVICES

INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack

Deep gate-all-around semiconductor device having germanium or group III-V active layer

TRENCH CONFINED EPITAXIALLY GROWN DEVICE LAYER(S)

Epitaxial buffer layers for group III-N transistors on silicon substrates

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

III-N material structure for gate-recessed transistors

Thermal management structure for low-power nonvolatile filamentary switch

Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in RRAM devices

Techniques for forming contacts to quantum well transistors

Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Strained channel region transistors employing source and drain stressors and systems including the same

Non-Planar Semiconductor Devices having Multi-Layered Compliant Substrates

Methods and structures to prevent sidewall defects during selective epitaxy

Techniques and configurations for stacking transistors of an integrated circuit device

Germanium-based quantum well devices

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

Deep gate-all-around semiconductor device having germanium or group III-V active layer

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

Methods of containing defects for non-silicon device engineering

Nanoscale structure with epitaxial film having a recessed bottom portion

Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack

Non-planar semiconductor device having active region with multi-dielectric gate stack

Techniques for forming contacts to quantum well transistors

Trench confined epitaxially grown device layer(s)

Methods of containing defects for non-silicon device engineering

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby

Defect transferred and lattice mismatched epitaxial film

Lattice mismatched hetero-epitaxial film

Epitaxial film on nanoscale structure

Epitaxial film growth on patterned substrate

III-N SEMICONDUCTOR-ON-SILICON STRUCTURES AND TECHNIQUES

Techniques for forming non-planar germanium quantum well devices

TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES

Epitaxial buffer layers for group III-N transistors on silicon substrates

Methods of containing defects for non-silicon device engineering

Trench confined epitaxially grown device layer(s)

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack

Non-planar semiconductor device having channel region with low band-gap cladding layer

Germanium-based quantum well devices

Techniques for forming non-planar germanium quantum well devices

Techniques and configuration for stacking transistors of an integrated circuit device

Preventing isolation leakage in III-V devices

Methods to enhance doping concentration in near-surface layers of semiconductors and methods of making same

III-N material structure for gate-recessed transistors

Strained channel region transistors employing source and drain stressors and systems including the same

Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Increasing carrier injection velocity for integrated circuit devices

Techniques for forming contacts to quantum well transistors

Non-planar germanium quantum well devices

Germanium-based quantum well devices

Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain

Forming conformal metallic platinum zinc films for semiconductor devices

Transistors with high concentration of boron doped germanium

HIGH INDIUM CONTENT TRANSISTOR CHANNELS

Tunnel field effect transistor

Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes

Methods of forming nickel sulphide film on a semiconductor device

Germanium-based quantum well devices

Multi-gate III-V quantum well structures

Conductivity improvements for III-V semiconductor devices

Techniques for forming contacts to quantum well transistors

Quantum well transistors with remote counter doping

Non-planar germanium quantum well devices

Increasing carrier injection velocity for integrated circuit devices

Techniques and configurations to impart strain to integrated circuit devices

Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same

Embedded memory cell and method of manufacturing same

Methods of forming nickel sulfide film on a semiconductor device

Methods of forming low interface resistance rare earth metal contacts and structures formed thereby

Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions

Sandwiched metal structure silicidation for enhanced contact

Method of forming self-aligned low resistance contact layer