Robert S. Chau

GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY

Metallization structures for stacked device connectivity and their methods of fabrication

GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY

Gallium nitride (GAN) three-dimensional integrated circuit technology

Method for fabricating transistor with thinned channel

Metallization structures for stacked device connectivity and their methods of fabrication

Multi-layer silicon/gallium nitride semiconductor

Low stray field magnetic memory

Perpendicular magnetic memory with symmetric fixed layers

Method for fabricating transistor with thinned channel

Resistive memory cells and precursors thereof, methods of making the same, and devices including the same

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

III-N epitaxial device structures on free standing silicon mesas

Semiconductor devices with raised doped crystalline structures

Spin-transfer torque memory (STTM) devices having magnetic contacts

Selective epitaxially grown III-V materials based devices

Methods and devices integrating III-N transistor circuitry with Si transistor circuitry

N-channel gallium nitride transistors

Wide band gap transistors on non-native semiconductor substrates

Perpendicular magnetic memory with filament conduction path

Integrated circuit die having reduced defect group III-nitride structures and methods associated therewith

Perpendicular magnetic memory with reduced switching current

Functional metal oxide based microelectronic devices

Rare earth metal and metal oxide electrode interfacing of oxide memory element in resistive random access memory cell

III-N epitaxial device structures on free standing silicon mesas

Stackable thin film memory

Semiconductor devices with raised doped crystalline structures

Gallium nitride (GaN) transistor structures on a substrate

Group III-N MEMS structures on a group IV substrate

Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer

Random number generator

Heteroepitaxial structures with high temperature stable substrate interface material

GaN devices on engineered silicon substrates

Resistive memory cells and precursors thereof, methods of making the same, and devices including the same

Method for fabricating transistor with thinned channel

Techniques for forming non-planar germanium quantum well devices

N-channel gallium nitride transistors

Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same

Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith

Amorphous seed layer for improved stability in perpendicular STTM stack

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Group III-N transistor on nanoscale template structures

WRITE CURRENT REDUCTION IN SPIN TRANSFER TORQUE MEMORY DEVICES

Techniques for forming contacts to quantum well transistors

Extreme high mobility CMOS logic

1S1R MEMORY CELLS INCORPORATING A BARRIER LAYER

Gallium nitride transistor having a source/drain structure including a single-crystal portion abutting a 2D electron gas

Resistive memory cells including localized filamentary channels, devices including the same, and methods of making the same

Fabrication of crystalline magnetic films for PSTTM applications

Magnetic diffusion barriers and filter in PSTTM MTJ construction

Methods and structures to prevent sidewall defects during selective epitaxy

TECHNIQUES FOR FILAMENT LOCALIZATION, EDGE EFFECT REDUCTION, AND FORMING/SWITCHING VOLTAGE REDUCTION IN RRAM DEVICES

CMOS circuits using n-channel and p-channel gallium nitride transistors

Wide band gap transistor on non-native semiconductor substrate

LOW SHEET RESISTANCE GaN CHANNEL ON Si SUBSTRATE USING InAlN AND AlGaN BI-LAYER CAPPING STACK

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

Integration of III-V devices on Si wafers

NANOSTRUCTURES AND NANOFEATURES WITH Si (111) PLANES ON Si (100) WAFERS FOR III-N EPITAXY

III-N devices in Si trenches

CONFIGURATIONS AND TECHNIQUES TO INCREASE INTERFACIAL ANISOTROPY OF MAGNETIC TUNNEL JUNCTIONS

Selective epitaxially grown III-V materials based devices

Field effect transistor structure with abrupt source/drain junctions

Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Semiconductor device having germanium active layer with underlying diffusion barrier layer

TRENCH CONFINED EPITAXIALLY GROWN DEVICE LAYER(S)

Making a defect free fin based device in lateral epitaxy overgrowth region

Variable gate width for gate all-around transistors

Oxide-based three-terminal resistive switching logic devices

Epitaxial buffer layers for group III-N transistors on silicon substrates

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

HIGH BREAKDOWN VOLTAGE III-N DEPLETION MODE MOS CAPACITORS

III-N material structure for gate-recessed transistors

Spin-transfer torque memory (STTM) devices having magnetic contacts

Non-planar quantum well device having interfacial layer and method of forming same

III-N transistors with enhanced breakdown voltage

Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

Transition metal dichalcogenide semiconductor assemblies

Germanium-based quantum well devices

SEMICONDUCTOR ASSEMBLIES WITH FLEXIBLE SUBSTRATES

Thermal management structure for low-power nonvolatile filamentary switch

Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in RRAM devices

III-N transistors with epitaxial layers providing steep subthreshold swing

Selective epitaxially grown III-V materials based devices

High breakdown voltage III-N depletion mode MOS capacitors

Techniques for forming non-planar resistive memory cells

Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer

Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof

FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR

Nonplanar III-N transistors with compositionally graded semiconductor channels

Semiconductor device structures and methods of forming semiconductor structures

Bi-axial tensile strained GE channel for CMOS

METHOD AND APPARATUS FOR FLEXIBLE ELECTRONIC COMMUNICATING DEVICE

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Self-storing and self-restoring non-volatile static random access memory

Techniques for forming contacts to quantum well transistors

Transistor structure with variable clad/core dimension for stress and bandgap

Group III-N transistors on nanoscale template structures

Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy

Selective epitaxially grown III-V materials based devices