Tigard, Oregon
United States
22
2025-09-18
The entities that hold a legal rights for patent applications filed by inventor Walczyk Joe:
Joe Walczyk from Tigard, US has applied for patents for these inventions. The list has both pending applications and granted patents:
3D DIE STACK REDISTRIBUTION LAYER FOR TOPSIDE POWER DELIVERY TO BACKSIDE DIE METALLIZATION IN MULTICHIP COMPOSITE DEVICES
#2 | 2024-06-20HYBRID BACKSIDE THERMAL STRUCTURES FOR ENHANCED IC PACKAGES
#3 | 2022-03-31Dual-sided socket device with corrugation structures and shield structures
#4 | 2021-12-30Additively manufactured structures for heat dissipation from integrated circuit devices
#5 | 2021-12-30Integrated circuit die packages including a contiguous heat spreader
#6 | 2021-12-02Hybrid thermal interface material (TIM) with reduced 3D thermal resistance
#7 | 2021-08-12Hybrid backside thermal structures for enhanced IC packages
#8 | 2021-08-05Slip-plane MEMs probe for high-density and fine pitch interconnects
#9 | 2021-03-25High density and fine pitch interconnect structures in an electric test apparatus
#10 | 2020-12-31DEFLECTED-PILLAR COMPOSITE COMPLIANT ELONGATED MICRO-STRUCTURE THERMAL INTERFACE MATERIALS
#11 | 2020-05-07Micro-coaxial wire interconnect architecture
#12 | 2020-04-02Slip-plane MEMS probe for high-density and fine pitch interconnects
#13 | 2020-01-23High density and fine pitch interconnect structures in an electric test apparatus
#14 | 2019-07-11High density and fine pitch interconnect structures in an electric test apparatus
#15 | 2019-07-04Electrical testing apparatus with lateral movement of a probe support substrate
#16 | 2019-07-04Massively-parallel micronozzle array for direct write electrodeposition of high-density microstructure arrays
#17 | 2019-03-28Conformable heat spreader
#18 | 2018-12-20Low profile edge clamp socket
#19 | 2018-10-04Shielded interconnect array
#20 | 2017-09-21ACTUATION MECHANISMS FOR ELECTRICAL INTERCONNECTIONS
#21 | 2014-06-12Actuation mechanisms for electrical interconnections
#22 | 2014-05-08Seal method for direct liquid cooling of probes used at first level interconnect
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