Steven P. Young

Compute dataflow architecture

Compute dataflow architecture

Power delivery network for active-on-active stacked integrated circuits

Multi-chip stacked devices

Redundancy scheme for multi-chip stacked devices

Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements

Distributed multi-die routing in a multi-chip module

Lut cascading circuit

Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer

Signed multiplier circuit utilizing a uniform array of logic blocks

Circuits for and methods of controlling power within an integrated circuit

Two gate pitch FPGA memory cell

Method and apparatus to reduce power segmentation overhead within an integrated circuit

Circuits for shifting bussed data

Method and apparatus for programmable device testing in stacked die applications

Programmable interconnect network

Self-timed single track circuit

Clock network architecture

Multiplier circuits with optional shift function

Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same

Error checking parity and syndrome of a block of data with relocated parity bits

Error checking parity and syndrome of a block of data with relocated parity bits

Configuration of a multi-die integrated circuit

Configuration of a multi-die integrated circuit

Clock distribution to facilitate gated clocks

Programmable integrated circuit with mirrored interconnect structure

Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies

Bus-based logic blocks with optional constant input

Hybrid integrated circuit device

Formation of columnar application specific circuitry using a columnar programmable device

Circuits for replicating self-timed logic

Methods and apparatus for device-specific configuration of a programmable integrated circuit

Error checking parity and syndrome of a block of data with relocated parity bits

Pipelined unidirectional programmable interconnect in an integrated circuit

Integrated circuit having embedded differential clock tree

Circuits for sharing self-timed logic

Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same

Circuits for enabling feedback paths in a self-timed integrated circuit

Merging data streams in a self-timed programmable integrated circuit

Gating logic circuits in a self-timed integrated circuit

Dynamically controlled output multiplexer circuits in a programmable integrated circuit

Circuits for fanning out data in a programmable self-timed integrated circuit

Multi-mode circuit in a self-timed integrated circuit

Bus-based logic blocks for self-timed integrated circuits

Cascading input structure for logic blocks in integrated circuits

Compute-centric architecture for integrated circuits

Circuit structures utilizing multiple voltage level inputs

Methods of initializing routing structures in integrated circuits

Implementing conditional statements in self-timed logic circuits

Integrated circuits with bus-based programmable interconnect structures

Regional signal-distribution network for an integrated circuit

Integrated circuits with novel handshake logic

Formation of a hybrid integrated circuit device

Structures and methods to avoiding hold time violations in a programmable logic device

Characterizing circuit performance by separating device and interconnect impact on signal delay

Methods of providing a family of related integrated circuits of different sizes

Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit

Yield-enhancing methods of providing a family of scaled integrated circuits

Formation of columnar application specific circuitry using a columnar programmable logic device

Single event upset in SRAM cells in FPGAs with high resistivity gate structures

Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies

Error checking parity and syndrome of a block of data with relocated parity bits

Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes

Interconnect driver circuits for dynamic logic

Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets

Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure

Regional signal-distribution network for an integrated circuit

Multi-product die configurable as two or more programmable integrated circuits of different logic capacities

Double data rate flip-flop

Method and system for configuring an integrated circuit

Structures and methods for avoiding hold time violations in a programmable logic device

Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets

Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability

Integrated circuit with programmable routing structure including straight and diagonal interconnect lines

Integrated circuit with programmable routing structure including diagonal interconnect lines

Efficient tile layout for a programmable logic device

Programmable logic block with carry chains providing lookahead functions of different lengths

Programmable lookup table with dual input and output terminals in RAM mode

Programmable logic block providing carry chain with programmable initialization values

Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure

Circuit for and method of implementing a content addressable memory in a programmable logic device

Memory device and method of transferring data in memory device

Efficient tile layout for a programmable logic device

Integrated circuit having fast interconnect paths between carry chain multiplexers and lookup tables

Integrated circuit having fast interconnect paths between memory elements and carry logic

Programmable integrated circuit providing efficient implementations of arithmetic functions

Programmable lookup table with dual input and output terminals in shift register mode

Programmable integrated circuit providing efficient implementations of wide logic functions

Integrated circuit having a programmable input structure with bounce capability

Integrated circuit interconnect structure having reduced coupling between interconnect lines

Integrated circuit having a programmable input structure with optional fanout capability

Programmable logic block having lookup table with partial output signal driving carry multiplexer

Columnar floorplan

Differential clock tree in an integrated circuit

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Characterizing circuit performance by separating device and interconnect impact on signal delay

Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability

Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets

Programmable multi-chip module