Trevor J. Bauer

PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT

Regularity of fabrics in programmable logic devices

Method and apparatus for programmable device testing in stacked die applications

Clock network architecture

Clock distribution to facilitate gated clocks

Programmable integrated circuit with mirrored interconnect structure

Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies

Formation of columnar application specific circuitry using a columnar programmable device

Regional signal-distribution network for an integrated circuit

Structures and methods to avoiding hold time violations in a programmable logic device

Methods of providing a family of related integrated circuits of different sizes

Yield-enhancing methods of providing a family of scaled integrated circuits

Formation of columnar application specific circuitry using a columnar programmable logic device

Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies

Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes

Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure

Regional signal-distribution network for an integrated circuit

Multi-product die configurable as two or more programmable integrated circuits of different logic capacities

Structures and methods for avoiding hold time violations in a programmable logic device

Programmable lookup table with dual input and output terminals in RAM mode

Programmable integrated circuit providing efficient implementations of arithmetic functions

Programmable lookup table with dual input and output terminals in shift register mode

Integrated circuit having a programmable input structure with bounce capability

Integrated circuit having a programmable input structure with optional fanout capability

Large crossbar switch implemented in FPGA

High-speed lookup table circuits and methods for programmable logic devices

Structures and methods of testing interconnect structures in programmable logic devices

Partial reconfiguration of a programmable logic device using an on-chip processor

Windowing circuit for aligning data and clock signals