Aloha, Oregon
United States
29
2017-07-13
The entities that hold a legal rights for patent applications filed by inventor Boggs Darrell D.:
Darrell D. Boggs from Aloha, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Lazy runahead operation for a microprocessor
#2 | 2014-10-23Dynamic configuration of processing pipeline based on determined type of fetched instruction
#3 | 2014-07-03Queued instruction re-dispatch after runahead
#4 | 2014-06-12INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION
#5 | 2014-06-12Lazy runahead operation for a microprocessor
#6 | 2014-05-15Managing potentially invalid results during runahead
#7 | 2011-09-29Method and apparatus for assigning thread priority in a processor or the like
#8 | 2011-05-12Method and apparatus for assigning thread priority in a processor or the like
#9 | 2009-03-12Method and apparatus for assigning thread priority in a processor or the like
#10 | 2008-11-18Method and apparatus for assigning thread priority in a processor or the like
#11 | 2007-05-31Bit field selection instruction
#12 | 2007-05-15Multi-threading techniques for a processor utilizing a replay queue
#13 | 2007-04-12Instruction packer for digital signal processor
#14 | 2007-04-03Processor with a replay system that includes a replay queue for improved throughput
#15 | 2007-02-20Prediction of load-store dependencies in a processing agent
#16 | 2006-12-28Programmable event driven yield mechanism which may activate service threads
#17 | 2006-09-28Rounding correction for add-shift-round instruction with dual-use source operand for DSP
#18 | 2006-09-28Add-shift-round instruction with dual-use source operand for DSP
#19 | 2006-09-28Instruction with dual-use source providing both an operand value and a control value
#20 | 2006-08-08Interface to a memory system for a processor having a replay system
#21 | 2006-05-23Method and apparatus for managing resources in a multithreaded processor
#22 | 2006-05-04Clip instruction for processor
#23 | 2006-05-04Clip-and-pack instruction for processor
#24 | 2006-03-07Determining whether thread fetch operation will be blocked due to processing of another thread
#25 | 2006-02-16Scalable matrix register file
#26 | 2006-01-19Microprocessor with branch target determination in decoded microinstruction code sequence
#27 | 2006-01-19Microprocessor with customer code store
#28 | 2005-12-27Breaking replay dependency loops in a processor using a rescheduled replay queue
#29 | 2005-04-05Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
765521 ⎘