Harold Pilo

Memory with hybrid write assist scheme

Memory with external clock synchronized operation

Output driver level-shifting latch circuit for dual-rail memory

At-speed synchronous write-through operation for testing two-port memory

REDUCED CIRCUIT AREA MEMORY DEVICE WITH A HALF-WORD MEMORY ARCHITECTURE

Memory clock level-shifting buffer with extended range

INTERFACE LEVEL-SHIFTER DUAL-RAIL MEMORY ARCHITECTURE

Power supply tracking circuitry for embedded memories

Scan chain compression for testing memory of a system on a chip

Pseudo-2-port memory with dual pre-charge circuits

Method and apparatus for memory noise-free wake-up protocol from power-down

Memory bypass function for a memory

Method and apparatus for integrated level-shifter and memory clock

Memory bypass function for a memory

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

TCAM field enable logic

Deep-sleep wake up for a memory device

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

SRAM circuit with increased write margin

Leakage-aware voltage regulation circuit and method

SRAM write-assisted operation with V-to-Vlevel shifting

Regulated power gating for growable memory

Fine granularity power gating

Vdiff max limiter in SRAMs for improved yield and power

Fine granularity power gating

Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method

Device and method for detecting resistive defect

Static random access memory (SRAM) write assist circuit with leakage suppression and level control

Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability

SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same

Single supply sub VDD bit-line precharge SRAM and method for level shifting

Structure and method for decoding read data-bus with column-steering redundancy

SRAM delay circuit that tracks bitcell characteristics

Column selectable self-biasing virtual voltages for SRAM write assist

Apparatus and method for implementing write assist for static random access memory arrays

System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture

STRUCTURE FOR IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS

Voltage Controlled Static Random Access Memory

Design structure for low overhead switched header power savings apparatus

System and method for implementing row redundancy with reduced access time and reduced device area

Device Threshold Calibration Through State Dependent Burnin

Temperature Dependent Bias for Minimal Stand-by Power in CMOS Circuits

Low overhead switched header power savings apparatus

METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS

Device threshold calibration through state dependent burn-in

Design structure for a current control mechanism for power networks and dynamic logic keeper circuits

Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same

Low overhead switched header power savings apparatus

Voltage controlled static random access memory

Voltage controlled static random access memory

Structure for power-efficient cache memory

Sense-amplifier assist (SAA) with power-reduction technique

Fully synchronous DLL with architected update window

Design structure for implementing dynamic data path with interlocked keeper and restore devices

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

SENSE-AMPLIFIER ASSIST (SAA) WITH POWER-REDUCTION TECHNIQUE

Voltage controlled static random access memory

Apparatus for implementing dynamic data path with interlocked keeper and restore devices

Method of improving fuse state detection and yield in semiconductor applications

POWER-EFFICIENT CACHE MEMORY SYSTEM AND METHOD THEREFOR

Method and apparatus for burn-in optimization

Circuit and method for controlling a standby voltage level of a memory

Voltage controlled static random access memory

Method and apparatus for burn-in optimization

SRAM cell using tunnel current loading devices

APPARATUS AND METHOD FOR SMALL SIGNAL SENSING IN AN SRAM CELL UTILIZING PFET ACCESS DEVICES

Delay-lock-loop with improved accuracy and range

Method and apparatus for initializing SRAM device during power-up

Method and system for maintaining uniform module junction temperature during burn-in

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

Method and apparatus for improving cycle time in a quad data rate SRAM device

System and method for implementing a micro-stepping delay chain for a delay locked loop

System and method for implementing a micro-stepping delay chain for a delay locked loop

Adaptive integrated circuit based on transistor current measurements

System and method for testing a column redundancy of an integrated circuit memory

Adaptive integrated circuit based on transistor current measurements

Scalable termination

Method for transparent updates of output driver impedance

DRAM-based separate I/O memory solution for communication applications

Method and circuit for precise timing of signals in an embedded DRAM array