San Jose, California
United States
62
2024-06-20
The entities that hold a legal rights for patent applications filed by inventor CHEN Chun:
Chun CHEN from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
HIGH-VOLTAGE TRANSISTOR WITH THIN HIGH-K METAL GATE AND METHOD OF FABRICATION THEREOF
#2 | 2024-01-04Method of forming high-voltage transistor with thin gate poly
#3 | 2021-09-23Method of forming high-voltage transistor with thin gate poly
#4 | 2021-05-06EMBEDDED NON-VOLATILE MEMORY DEVICE AND FABRICATION METHOD OF THE SAME
#5 | 2021-04-08Split gate charge trapping memory cells having different select gate and memory gate heights
#6 | 2021-03-25Memory first process flow and device
#7 | 2020-09-24Suppression of program disturb with bit line and select gate voltage regulation
#8 | 2019-12-19Memory first process flow and device
#9 | 2019-10-03Method of Forming High-Voltage Transistor with Thin Gate Poly
#10 | 2019-09-12Suppression of program disturb with bit line and select gate voltage regulation
#11 | 2019-06-27Multi-layer inter-gate dielectric structure and method of manufacturing thereof
#12 | 2019-06-27Non-volatile memory array with memory gate line and source line scrambling
#13 | 2019-01-24Method of forming high-voltage transistor with thin gate poly
#14 | 2019-01-24Embedded non-volatile memory device and fabrication method of the same
#15 | 2018-12-20Memory first process flow and device
#16 | 2018-12-13Split-gate semiconductor device with L-shaped gate
#17 | 2018-11-27Three dimensional capacitor
#18 | 2018-11-08Charge trapping split gate device and method of fabricating same
#19 | 2018-09-13Non-volatile memory array with memory gate line and source line scrambling
#20 | 2018-07-05Suppression of program disturb with bit line and select gate voltage regulation
#21 | 2018-06-14Split-gate flash cell formed on recessed substrate
#22 | 2018-06-14Non-volatile memory array with memory gate line and source line scrambling
#23 | 2018-01-30Suppression of program disturb with bit line and select gate voltage regulation
#24 | 2017-12-26Split-gate flash cell formed on recessed substrate
#25 | 2017-09-14Multi-layer inter-gate dielectric structure and method of manufacturing thereof
#26 | 2017-07-06Split gate charge trapping memory cells having different select gate and memory gate heights
#27 | 2017-06-08Split-gate semiconductor device with L-shaped gate
#28 | 2017-05-18Memory first process flow and device
#29 | 2016-10-20Three-dimensional charge trapping NAND cell with discrete charge trapping film
#30 | 2016-10-06Memory first process flow and device
#31 | 2016-07-28Gate Formation Memory by Planarization
#32 | 2016-07-28Integrated Circuits with Non-Volatile Memory and Methods for Manufacture
#33 | 2016-04-21Charge trapping split gate embedded flash memory and associated methods
#34 | 2016-02-04Split-gate semiconductor device with L-shaped gate
#35 | 2015-10-08Use disposable gate cap to form transistors, and split gate charge trapping memory cells
#36 | 2015-07-09MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE
#37 | 2015-07-02Formation of gate sidewall structure
#38 | 2015-06-25Gate formation memory by planarization
#39 | 2015-06-18Process for forming edge wordline implants adjacent edge wordlines
#40 | 2015-04-23Three-dimensional charge trapping NAND cell with discrete charge trapping film
#41 | 2015-01-29Integrated circuits with non-volatile memory and methods for manufacture
#42 | 2014-12-18Non-volatile FINFET memory array and manufacturing method thereof
#43 | 2014-11-13HIGH VOLTAGE GATE FORMATION
#44 | 2014-06-19Charge trapping split gate device and method of fabricating same
#45 | 2014-06-19THREE DIMENSIONAL CAPACITOR
#46 | 2014-06-19Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells
#47 | 2014-06-19Charge Trapping Split Gate Embedded Flash Memory and Associated Methods
#48 | 2014-06-19Memory first process flow and device
#49 | 2014-06-19Integrated circuits with non-volatile memory and methods for manufacture
#50 | 2014-06-19High voltage gate formation
#51 | 2014-06-19Process charging protection for split gate charge trapping flash
#52 | 2014-06-19Memory gate landing pad made from dummy features
#53 | 2014-05-29Non-volatile FINFET memory device and manufacturing method thereof
#54 | 2012-07-19Methods for forming a memory cell having a top oxide spacer
#55 | 2012-07-19Non-volatile FINFET memory array and manufacturing method thereof
#56 | 2012-07-05Memory with extended charge trapping layer
#57 | 2012-06-07METHOD AND APPARATUS FOR NAND MEMORY WITH RECESSED SOURCE/DRAIN REGION
#58 | 2012-03-08Method and device employing polysilicon scaling
#59 | 2011-09-29Methods for forming a memory cell having a top oxide spacer
#60 | 2011-09-15NAND ARRAY SOURCE/DRAIN DOPING SCHEME
#61 | 2011-09-15Non-volatile FINFET memory device and manufacturing method thereof
#62 | 2010-08-19Method and device employing polysilicon scaling
779022 ⎘