SPANSION LLC

Device and method for resisting non-invasive attacks

Temperature detection circuit and temperature measurement circuit

Protecting circuit and integrated circuit

Charge-trapping memory device

Simultaneous programming of many bits in flash memory

Overlaid erase block mapping

System-on-chip verification

Integration of semiconductor memory cells and logic cells

Crystal oscillation circuit

Control apparatus, and control method for buck-boost power supply with two primary switches

Detecting the drift of the data valid window in a transaction

Booting an application from multiple memories

Methods, circuits, devices and systems for integrated circuit voltage level shifting

Methods, circuits, devices and systems for sensing an NVM cell

Buried trench isolation in integrated circuits

Memory access bases on erase cycle time

Memory subsystem with wrapped-to-continuous read

Formation of gate sidewall structure

Gate formation memory by planarization

CT-NOR differential bitline sensing architecture

Process for forming edge wordline implants adjacent edge wordlines

Increasing lithographic depth of focus window using wafer topography

Generation of wake-up words

Auto resume of irregular erase stoppage of a memory sector

Output switching circuit

Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same

Multiple phase-shift photomask and semiconductor manufacturing method

Three-dimensional charge trapping NAND cell with discrete charge trapping film

Method for providing read data flow control or error reporting using a read data strobe

Memory program upon system failure

Hidden Markov Model processing engine

Multi-pass soft programming

Spacer formation with straight sidewall

Ion implantation-assisted etch-back process for improving spacer shape and spacer width control

Methods circuits apparatuses and systems for providing current to a non-volatile memory array and non-volatile memory devices produced accordingly

Self-aligned trench isolation in integrated circuits

Methods circuits apparatuses and systems for sensing a logical state of a non-volatile memory cell and non-volatile memory devices produced accordingly

Method of chip positioning for multi-chip packaging

Apparatus and method for smart VCC trip point design for testability

System with memory having voltage applying unit

Non-volatile FINFET memory array and manufacturing method thereof

Controlling the latchup effect

Metal-insualtor-metal (MIM) device and method of formation thereof

Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors

Die seal layout for VFTL dual damascene in a semiconductor device

System and method for manufacturing self-aligned STI with single poly

Charge-trap NOR with silicon-rich nitride as a charge trap layer

Restoring ECC syndrome in non-volatile memory devices

DC-DC converter with adaptive phase compensation controller

Combining of results from multiple decoders

Authentication for recognition systems

Modified local segmented self-boosting of memory cell channels

Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof

Node system and supervisory node

Method of manufacturing a semiconductor device having a chip mounted on an interposer

Mitigate flash write latency and bandwidth limitation by preferentially storing frequently written sectors in cache memory during a databurst

Host/client system having a scalable serial bus interface

Contact configuration for undertaking tests on circuit board

Data pattern analysis

Flash memory cells having trenched storage elements

System and method for improving reliability in a semiconductor device

Memory buffering system that improves read/write performance and provides low latency for mobile systems

Non-volatile memory device with an EPLI comparator

Variable read latency on a serial memory bus

Non-Volatile memory with silicided bit line contacts

Convex shaped thin-film transistor device having elongated channel over insulating layer

Semiconductor device and control method of the same

Control circuit of step-down DC-DC converter, control circuit of step-up DC-DC converter and step-up/step-down DC-DC converter

Debug control circuit

Buried hard mask for embedded semiconductor device patterning

Programmable and flexible reference cell selection method for memory devices

Multi-chip package assembly with improved bond wire separation

For test (DFT) read speed through transition detector in built-in self-test (BIST) sort

Phoneme score accelerator

Histogram based pre-pruning scheme for active HMMS

Hybrid hashing scheme for active HMMS

Memory device with internal combination logic

Chip positioning in multi-chip package

Memory device with source-side sensing

System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device

Charge trapping split gate device and method of fabricating same

Semiconductor device having element separation region formed from a recess-free trench