Sven Beyer

IC structure with MFMIS memory cell and CMOS transistor

Structures for a ferroelectric field-effect transistor and related methods

Structure including a cross-bar router and method

Ferro-FET device with buried buffer/ferroelectric layer stack

Transistor element including a buried insulating layer having enhanced functionality

Programmable logic elements and methods of operating the same

Flash memory device

NVM device in SOI technology and method of fabricating an according device

Flash memory device

Communicating optical signals between stacked dies

Methods for forming integrated circuits that include a dummy gate structure

Integrated circuit including a dummy gate structure and method for the formation thereof

Semiconductor device with a memory device and a high-K metal gate transistor

Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure

Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure

Semiconductor structure including a nonvolatile memory cell and method for the formation thereof

BULEX contacts in advanced FDSOI techniques

Capacitor structure and method of forming a capacitor structure

Die-die stacking

Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure including a nonvolatile memory cell

MEANDER RESISTOR

ROBUST POST-GATE SPACER PROCESSING AND DEVICE

MEANDER RESISTOR

Methods for fabricating integrated circuits with fully silicided gate electrode structures

Methods for fabricating FinFET integrated circuits using laser interference lithography techniques

SEMICONDUCTOR DEVICE INCLUDING A TRANSISTOR HAVING A LOW DOPED DRIFT REGION AND METHOD FOR THE FORMATION THEREOF

SUPERIOR INTEGRITY OF A HIGH-K GATE STACK BY FORMING A CONTROLLED UNDERCUT ON THE BASIS OF A WET CHEMISTRY

Gate electrode with a shrink spacer

Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material

Semiconductor device comprising a stacked die configuration including an integrated peltier element

Method of forming a semiconductor structure including a wet etch process for removing silicon nitride

Work function adjustment in a high-K gate electrode structure after transistor fabrication by using lanthanum

Field effect transistors for a flash memory comprising a self-aligned charge storage region

METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING RAISED DRAIN AND SOURCE REGIONS AND CORRESPONDING SEMICONDUCTOR DEVICE

Method for making high-K metal gate electrode structures by separate removal of placeholder materials

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure

Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface Layer

High-K metal gate electrode structures formed by early cap layer adaptation

Method of forming spacers that provide enhanced protection for gate electrode structures

Dual Cavity Etch for Embedded Stressor Regions

SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION

High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Superior integrity of high-k metal gate stacks by capping STI regions

Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization

Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping

Patterning of a Stressed Dielectric Material in a Contact Level Without Using an Underlying Etch Stop Layer

Superior integrity of a high-K gate stack by forming a controlled undercut on the basis of a wet chemistry

Gate electrodes of a semiconductor device formed by a hard mask and double exposure in combination with a shrink spacer

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

Semiconductor device comprising a stacked die configuration including an integrated Peltier element

Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach

Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner

Field effect transistors for a flash memory comprising a self-aligned charge storage region

Strain memorization in strained SOI substrates of semiconductor devices

Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials

Transistor Comprising a Buried High-K Metal Gate Electrode Structure

Contact bars with reduced fringing capacitance in a semiconductor device

ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION

Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition

High-K metal gate electrode structures formed at different process stages of a semiconductor device

Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors

Enhanced confinement of sensitive materials of a high-K metal gate electrode structure

Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime

Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation

Work function adjustment in high-k gate stacks for devices of different threshold voltage

REDUCING THE SERIES RESISTANCE IN SOPHISTICATED TRANSISTORS BY EMBEDDING METAL SILICIDE CONTACT REGIONS RELIABLY INTO HIGHLY DOPED SEMICONDUCTOR MATERIAL

High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer

HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS IN TRANSISTORS OF DIFFERENT CONDUCTIVITY TYPE

Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers

TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT

Superior fill conditions in a replacement gate approach by corner rounding prior to completely removing a placeholder material

Optical signal transfer in a semiconductor device by using monolithic opto-electronic components

Maintaining integrity of a high-K gate stack by passivation using an oxygen plasma

Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning

Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing

Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization

Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy

Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material

Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch

Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum

Short channel transistor with reduced length variation by using amorphous electrode material during implantation

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure

Multiple gate transistor having homogenously silicided fin end portions

Contacts and vias of a semiconductor device formed by a hard mask and double exposure

TRANSISTOR HAVING A STRAINED CHANNEL REGION CAUSED BY HYDROGEN-INDUCED LATTICE DEFORMATION

Two step optical planarizing layer etch

Semiconductor device comprising isolation trenches inducing different types of strain

Semiconductor device comprising a metal gate stack of reduced height and method of forming the same

METHOD FOR FORMING A DEEP TRENCH IN AN SOI DEVICE BY REDUCING THE SHIELDING EFFECT OF THE ACTIVE LAYER DURING THE DEEP TRENCH ETCH PROCESS

Methods for fabricating an integrated circuit

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

Method of making a semiconductor device comprising isolation trenches inducing different types of strain

Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor

Field effect transistor and method of forming a field effect transistor

Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same