Inventor profile of:

Mac D. Apodaca

City:

San Jose, California

Country:

United States

Published Applications:

31

Last publication date:

2020-11-19

Top Assignees for applications by Mac D. Apodaca

The entities that hold a legal rights for patent applications filed by inventor Apodaca Mac D.:

Recent patent applications by Apodaca Mac D.

Mac D. Apodaca from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-11-19
US20200365204A1
Physics

Set/reset methods for crystallization improvement in phase change memories

#2 | 2020-11-19
US20200365203A1
Physics

Set/reset methods for crystallization improvement in phase change memories

#3 | 2020-10-29
US20200342926A1
Physics

ONE SELECTOR ONE RESISTOR MRAM CROSSPOINT MEMORY ARRAY FABRICATION METHODS

#4 | 2019-02-28
US20190067374A1
Electricity

Non-volatile memory system with serially connected non-volatile reversible resistance-switching memory cells

#5 | 2019-02-28
US20190067370A1
Electricity

Process for fabricating three dimensional non-volatile memory system

#6 | 2019-02-28
US20190067369A1
Electricity

Memory cell for non-volatile memory system

#7 | 2019-02-28
US20190066763A1
Physics

Chip with phase change memory and magnetoresistive random access memory

#8 | 2018-12-04
US15693376
Electricity

Phase change memory electrode with multiple thermal interfaces

#9 | 2018-07-26
US20180212147A1
Electricity

Nanoparticle-based resistive memory device and methods for manufacturing the same

#10 | 2018-06-07
US20180158870A1
Electricity

Thermal management of selector

#11 | 2018-02-01
US20180033825A1
Electricity

Thermal management of selector

#12 | 2018-01-04
US20180004264A1
Physics

INTEGRATED CIRCUIT POWER DISTRIBUTION WITH THRESHOLD SWITCHES

#13 | 2017-10-19
US20170301732A1
Electricity

Dual OTS memory cell selection means and method

#14 | 2017-10-19
US20170301729A1
Electricity

Nano-imprinted self-aligned multi-level processing method

#15 | 2017-10-19
US20170301677A1
Electricity

Nano-imprinted self-aligned multi-level processing method

#16 | 2017-10-05
US20170287907A1
Electricity

3D cross-point memory manufacturing process having limited lithography steps

#17 | 2017-10-05
US20170287906A1
Electricity

3D cross-point memory manufacturing process having limited lithography steps

#18 | 2017-09-28
US20170279043A1
Electricity

Method to fabricate discrete vertical transistors

#19 | 2017-09-14
US20170263314A1
Physics

Memory cell located pulse generator

#20 | 2017-08-15
US15080525
Electricity

3D cross-point memory device

#21 | 2016-12-22
US20160372659A1
Electricity

SELF-ALIGNED MEMORY CELL CONTACT

#22 | 2016-12-01
US20160351627A1
Electricity

Embedded non-volatile memory

#23 | 2016-06-02
US20160155636A1
Electricity

Deposition method for planar surfaces

#24 | 2016-01-21
US20160020391A1
Electricity

Self-aligned memory cell contact

#25 | 2016-01-21
US20160020253A1
Electricity

Embedded non-volatile memory

#26 | 2016-01-14
US20160012889A1
Physics

Multiple bit per cell dual-alloy GST memory elements

#27 | 2015-12-24
US20150372226A1
Electricity

VARIABLE SELECTIVITY SILICON GROWTH PROCESS

#28 | 2014-11-13
US20140335669A1
Electricity

Embedded non-volatile memory

#29 | 2014-06-12
US20140158963A1
Electricity

Embedded non-volatile memory

#30 | 2010-04-22
US20100096610A1
Electricity

PHASE-CHANGE MATERIAL MEMORY CELL

#31 | 2010-02-25
US20100047995A1
Electricity

Method for forming self-aligned phase-change semiconductor diode memory

InventorID:

792403 ⎘