Guy Lynn Guthrie

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Method for flagging data modification during a virtual machine backup

System for flagging data modification during a virtual machine backup

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Dynamic detection and correction of incorrect lock and atomic update hint bits

Dynamic detection and software correction of incorrect lock and atomic update hint bits

Virtual machine backup

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Virtual machine backup

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Techniques for logging addresses of high-availability data via a non-blocking channel

Logging addresses of high-availability data

Cache configured to log addresses of high-availability data via a non-blocking channel

Cache configured to log addresses of high-availability data

Moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache

Techniques for moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache

Virtual machine failover

Information handling system with immediate scheduling of load operations

Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow

Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow

Specifying an access hint for prefetching partial cache block data in a cache hierarchy

Information handling system with immediate scheduling of load operations and fine-grained access to cache memory

Load request scheduling in a cache hierarchy

Processor system and methods of triggering a block move using a system bus write command initiated by user code

Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline

Cache coherent I/O communication

Multiprocessor system with retry-less TLBI protocol

Chaining multiple smaller store queue entries for more efficient store queue usage

Enhanced processor virtualization mechanism via saving and restoring soft processor/system states

Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation

L2 cache controller with slice directory and unified cache structure

Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing

Enhanced processor virtualization mechanism via saving and restoring soft processor/system states

System bus structure for large L2 cache array topology with different latency domains

System bus structure for large L2 cache array topology with different latency domains

Pipelining D states for MRU steerage during MRU-LRU member allocation

Cache member protection with partial make MRU allocation

Method for Priority Scheduling and Priority Dispatching of Store Conditional Operations in a Store Queue

System and method for completing full updates to entire cache lines stores with address-only bus operations

Method for priority scheduling and priority dispatching of store conditional operations in a store queue

Data processing system and method for efficient L3 cache directory management

Data processing system and method for efficient L3 cache directory management

L2 cache array topology for large cache with different latency domains

Efficient coherency communication utilizing an IG coherency state

Victim cache using direct intervention

Data processing system and method for handling castout collisions

Data processing system and method for efficient communication utilizing an Tn and Ten coherency states

Data processing system and method for efficient coherency communication utilizing coherency domain indicators

Cache directory array recovery mechanism to support special ECC stuck bit matrix

Cross partition sharing of state information

System and method of responding to a cache read error with a temporary cache directory column delete

Managing processor architected state upon an interrupt

Cache allocation mechanism for biasing subsequent allocations based upon cache directory state

Cache memory direct intervention

Victim cache using direct intervention

Data processing system and method for efficient L3 cache directory management

Data processing system and method for efficient communication utilizing an Ig coherency state

Data processing system and method for efficient coherency communication utilizing coherency domain indicators

Data processing system and method for efficient communication utilizing an Tn and Ten coherency states

Data processing system and method for efficient coherency communication utilizing coherency domains

Data processing system and method for handling castout collisions

Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation

Cache member protection with partial make MRU allocation

Pipelining D states for MRU steerage during MRU/LRU member allocation

Half-good mode for large L2 cache array topology with different latency domains

L2 cache controller with slice directory and unified cache structure

System and method of re-ordering store operations within a processor

L2 cache array topology for large cache with different latency domains

System bus structure for large L2 cache array topology with different latency domains

Multiprocessor system supporting multiple outstanding TLBI operations per partition

Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism

Data cache scrub mechanism for large L2/L3 data cache structures

Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability

Data processing system providing hardware acceleration of input/output (I/O) communication

Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems

Method for priority scheduling and priority dispatching of store conditional operations in a store queue

Processor, data processing system and method for synchronzing access to data in shared memory

Processor, data processing system and method for synchronizing access to data in shared memory

Processor, data processing system and method for synchronizing access to data in shared memory

Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members

Dynamically managing saved processor soft states

Processor virtualization mechanism via an enhanced restoration of hard architected states

Acceleration of input/output (I/O) communication through improved address translation

Layered local cache with lower level cache optimizing allocation mechanism

Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted

System and method for completing updates to entire cache lines with address-only bus operations

System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture

System and method for reducing contention in a multi-sectored cache

Asynchronous non-blocking snoop invalidation

System bus read data transfers with data ordering control bits

Method and apparatus for transmitting packets within a symmetric multiprocessor system

Speculative execution of instructions and processes before completion of preceding barrier operations

Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes

System bus read data transfers with data ordering control bits

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response