Inventor profile of:

Markus Dinkel

City:

Unterhaching

Country:

Germany

Published Applications:

28

Last publication date:

2025-09-11

Top Assignees for applications by Markus Dinkel

The entities that hold a legal rights for patent applications filed by inventor Dinkel Markus:

Recent patent applications by Dinkel Markus

Markus Dinkel from Unterhaching, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-09-11
US20250286011A1
Electricity

SEMICONDUCTOR PACKAGE WITH HYBRID INTERCONNECT CLIP

#2 | 2025-07-03
US20250218914A1
Electricity

PACKAGE WITH COMPONENT-CARRYING INTERMEDIATE STRUCTURE AND ADDITIONAL CARRIER HAVING REFERENCE POTENTIAL STRUCTURE

#3 | 2023-11-30
US20230387068A1
Electricity

Method of manufacturing a package using a clip having at least one locking recess

#4 | 2023-07-20
US20230230903A1
Electricity

SEMICONDUCTOR CHIP, CHIP SYSTEM, METHOD OF FORMING A SEMICONDUCTOR CHIP, AND METHOD OF FORMING A CHIP SYSTEM

#5 | 2023-06-15
US20230187326A1
Electricity

Semiconductor device having a carrier, semiconductor chip packages mounted on the carrier and a cooling element

#6 | 2023-03-30
US20230095545A1
Electricity

Semiconductor Packages and Methods for Manufacturing Thereof

#7 | 2022-07-21
US20220230941A1
Electricity

Method of fabricating a semiconductor package

#8 | 2021-02-04
US20210035876A1
Electricity

SEMICONDUCTOR PACKAGE INCLUDING A CAVITY IN ITS PACKAGE BODY

#9 | 2021-01-21
US20210020553A1
Electricity

Leadframe leads having fully plated end faces

#10 | 2020-11-19
US20200365549A1
Electricity

Clip having locking recess for connecting an electronic component with a carrier in a package

#11 | 2020-10-15
US20200328141A1
Electricity

Plurality of transistor packages with exposed source and drain contacts mounted on a carrier

#12 | 2020-05-07
US20200144150A1
Electricity

Method of producing an SMD package with top side cooling

#13 | 2020-04-30
US20200135619A1
Electricity

Semiconductor package and method of fabricating a semiconductor package

#14 | 2019-03-14
US20190080980A1
Electricity

SMD package with top side cooling

#15 | 2018-10-18
US20180301398A1
Electricity

SMD package with flat contacts to prevent bottleneck

#16 | 2017-10-05
US20170287820A1
Electricity

Semiconductor package having a source-down configured transistor die and a drain-down configured transistor die

#17 | 2017-09-21
US20170271246A1
Electricity

Leadframe leads having fully plated end faces

#18 | 2016-12-29
US20160380181A1
Electricity

Semiconductor package with integrated magnetic field sensor

#19 | 2016-12-29
US20160379966A1
Electricity

Power package with integrated magnetic field sensor

#20 | 2016-12-29
US20160377689A1
Physics

Multi-functional interconnect module and carrier with multi-functional interconnect module attached thereto

#21 | 2016-12-01
US20160351475A1
Electricity

Semiconductor device including lead frames with downset

#22 | 2016-11-10
US20160329260A1
Electricity

Electronic device including a metal substrate and a semiconductor module embedded in a laminate

#23 | 2016-04-21
US20160113127A1
Electricity

Electronic module having an electrically insulating structure with material having a low modulus of elasticity

#24 | 2016-02-18
US20160050768A1
Electricity

Module with integrated power electronic circuitry and logic circuitry

#25 | 2016-01-14
US20160013176A1
Electricity

Semiconductor device and method for manufacturing a semiconductor device

#26 | 2015-03-05
US20150062825A1
Electricity

Overmolded substrate-chip arrangement with heat sink

#27 | 2014-06-19
US20140167044A1
Electricity

Semiconductor device and method for manufacturing a semiconductor device

#28 | 2014-06-19
US20140167043A1
Electricity

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

InventorID:

802123 ⎘