Shingle Springs, California
United States
115
2026-06-11
The entities that hold a legal rights for patent applications filed by inventor Castro Hernan A.:
Hernan A. Castro from Shingle Springs, US has applied for patents for these inventions. The list has both pending applications and granted patents:
THREE-STATE PROGRAMMING OF MEMORY CELLS
#2 | 2026-01-15MEMORY ARRAY DECODING AND INTERCONNECTS
#3 | 2025-05-22PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO PRE-SYNAPTIC SPIKE SIGNALS, AND RELATED METHODS AND SYSTEMS
#4 | 2024-10-17PULSE BASED MULTI-LEVEL CELL PROGRAMMING
#5 | 2024-10-03PROCESSING-IN-MEMORY OPERATIONS, AND RELATED APPARATUSES, SYSTEMS, AND METHODS
#6 | 2024-09-19MULTI-STATE PROGRAMMING OF MEMORY CELLS
#7 | 2024-08-29CROSS-POINT MEMORY ARRAY WITH ACCESS LINES
#8 | 2024-08-15PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO PRE-SYNAPTIC SPIKE SIGNALS, AND RELATED METHODS AND SYSTEMS
#9 | 2024-07-11THIN FILM TRANSISTORS AND RELATED FABRICATION TECHNIQUES
#10 | 2024-07-11PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO SPIKING EVENTS, AND RELATED METHODS, SYSTEMS AND DEVICES
#11 | 2024-06-06MEMORY ARRAY DECODING AND INTERCONNECTS
#12 | 2024-04-11THREE-STATE PROGRAMMING OF MEMORY CELLS
#13 | 2023-12-07INTERFACES BETWEEN HIGHER VOLTAGE AND LOWER VOLTAGE WAFERS AND RELATED APPARATUSES AND METHODS
#14 | 2023-11-09Pulse based multi-level cell programming
#15 | 2023-09-07SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS
#16 | 2023-09-07SEMICONDUCTOR MEMORY DIES BONDED TO LOGIC DIES AND ASSOCIATED SYSTEMS AND METHODS
#17 | 2023-04-27Edgeless memory clusters
#18 | 2023-04-06Methods of performing processing-in-memory operations, and related devices and systems
#19 | 2023-04-06Memory array decoding and interconnects
#20 | 2023-03-09CONNECTIONS FOR MEMORY ELECTRODE LINES
#21 | 2022-10-25Edgeless memory clusters
#22 | 2022-08-04Three-state programming of memory cells
#23 | 2022-06-16Techniques for programming a memory cell
#24 | 2022-03-17Interconnection for memory electrodes
#25 | 2022-03-10Multi-state programming of memory cells
#26 | 2021-12-23Methods of performing processing-in-memory operations, and related devices and systems
#27 | 2021-09-16Thin film transistors and related fabrication techniques
#28 | 2021-09-09Memory device architecture
#29 | 2021-07-01Multi-state programming of memory cells
#30 | 2021-07-01Three-state programming of memory cells
#31 | 2021-06-03Cross-point memory array and related fabrication techniques
#32 | 2021-04-01Cross-point memory array with access lines
#33 | 2021-04-01Comparing input data to stored data
#34 | 2021-03-11Performing processing-in-memory operations related to pre-synaptic spike signals, and related methods and systems
#35 | 2021-03-11Performing processing-in-memory operations related to spiking events, and related methods, systems and devices
#36 | 2021-02-04Memory array decoding and interconnects
#37 | 2021-01-21Stored charge use in cross-point memory
#38 | 2021-01-07Operations on memory cells
#39 | 2021-01-07Techniques for programming a memory cell
#40 | 2020-10-29Connections for memory electrode lines
#41 | 2020-10-08Buried lines and related fabrication techniques
#42 | 2020-08-13Interconnection for memory electrodes
#43 | 2020-07-09Apparatuses, devices and methods for sensing a snapback event in a circuit
#44 | 2020-06-18Thin film transistors and related fabrication techniques
#45 | 2020-06-18Memory array decoding and interconnects
#46 | 2020-05-14Memory device architecture
#47 | 2020-02-27Techniques for programming a memory cell
#48 | 2020-02-13Apparatuses and methods for bi-directional access of crosspoint arrays
#49 | 2020-01-09Pulsed integrator and memory techniques for determining a state of a memory cell
#50 | 2020-01-09Memory tile access and selection patterns
#51 | 2019-11-28Operational signals generated from capacitive stored charge
#52 | 2019-11-07Operations on memory cells
#53 | 2019-11-07Accessing memory cells in parallel in a cross-point array
#54 | 2019-10-31Comparing input data to stored data
#55 | 2019-10-24Buried lines and related fabrication techniques
#56 | 2019-10-24Cross-point memory array and related fabrication techniques
#57 | 2019-10-24Cross-point memory array and related fabrication techniques
#58 | 2019-05-30Operations on memory cells
#59 | 2019-05-30Comparing input data to stored data
#60 | 2019-05-23Pulsed integrator and memory techniques
#61 | 2019-02-07Reset refresh techniques for self-selecting memory
#62 | 2019-01-10Memory device architecture
#63 | 2019-01-10Memory device architecture
#64 | 2019-01-10Apparatuses, devices and methods for sensing a snapback event in a circuit
#65 | 2019-01-10Interconnection for memory electrodes
#66 | 2019-01-03Compensation for threshold voltage variation of memory cell components
#67 | 2018-12-27Connections for memory electrode lines
#68 | 2018-11-15Path isolation in a memory device
#69 | 2018-10-04Memory tile access and selection patterns
#70 | 2018-07-05Accessing memory cells in parallel in a cross-point array
#71 | 2018-05-31Apparatuses for modulating threshold voltages of memory cells
#72 | 2018-03-22Compensation for threshold voltage variation of memory cell components
#73 | 2017-12-14Memory device architecture
#74 | 2017-12-14Apparatuses, devices and methods for sensing a snapback event in a circuit
#75 | 2017-12-07Apparatuses and methods for bi-directional access of cross-point arrays
#76 | 2017-12-07Accessing memory cells in parallel in a cross-point array
#77 | 2017-12-07Interconnection for memory electrodes
#78 | 2017-11-16Path isolation in a memory device
#79 | 2017-10-26Operational signals generated from capacitive stored charge
#80 | 2017-10-10Compensation for threshold voltage variation of memory cell components
#81 | 2017-08-03Methods and apparatuses for modulating threshold voltages of memory cells
#82 | 2017-07-06Memory tile access and selection patterns
#83 | 2017-05-16Methods and apparatuses for modulating threshold voltages of memory cells
#84 | 2017-03-09Path isolation in a memory device
#85 | 2017-02-02Connections for memory electrode lines
#86 | 2016-12-01Interconnection for memory electrodes
#87 | 2016-10-20Memory tile access and selection patterns
#88 | 2016-09-22Apparatuses and methods for bi-directional access of cross-point arrays
#89 | 2016-09-08Connections for memory electrode lines
#90 | 2016-08-18Accessing memory cells in parallel in a cross-point array
#91 | 2016-08-04Path isolation in a memory device
#92 | 2016-05-12Connections for memory electrode lines
#93 | 2016-03-10Operational signals generated from capacitive stored charge
#94 | 2016-02-04Memory device architecture
#95 | 2015-11-12Apparatuses and methods for bi-directional access of cross-point arrays
#96 | 2015-08-06Metallization scheme for integrated circuit
#97 | 2015-06-25Path isolation in a memory device
#98 | 2015-03-12Accessing memory cells in parallel in a cross-point array
#99 | 2015-03-12Interconnection for memory electrodes
#100 | 2015-03-05Memory controller for reducing capacitive coupling in a cross-point memory
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