Inventor profile of:

Roberto Gastaldi

City:

Agrate Brianza

Country:

Italy

Published Applications:

30

Last publication date:

2019-07-18

Top Assignees for applications by Roberto Gastaldi

The entities that hold a legal rights for patent applications filed by inventor Gastaldi Roberto:

Recent patent applications by Gastaldi Roberto

Roberto Gastaldi from Agrate Brianza, IT has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-07-18
US20190221264A1
Physics

Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells

#2 | 2018-12-20
US20180366189A1
Physics

Refresh architecture and algorithm for non-volatile memories

#3 | 2017-12-07
US20170352414A1
Physics

Phase change memory device

#4 | 2017-11-02
US20170316831A1
Physics

Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells

#5 | 2017-08-24
US20170243644A1
Physics

Refresh architecture and algorithm for non-volatile memories

#6 | 2015-10-22
US20150302924A1
Physics

Refresh architecture and algorithm for non-volatile memories

#7 | 2015-10-08
US20150287458A1
Physics

Phase change memory device

#8 | 2015-09-10
US20150255152A1
Physics

Resistance variable memory sensing

#9 | 2015-04-09
US20150098269A1
Physics

Read distribution management for phase change memory

#10 | 2014-10-30
US20140321191A1
Physics

Resistance variable memory sensing

#11 | 2014-05-22
US20140140134A1
Physics

Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells

#12 | 2014-02-06
US20140036583A1
Physics

Phase change memory device

#13 | 2013-10-17
US20130272063A1
Physics

Read distribution management for phase change memory

#14 | 2013-01-03
US20130003451A1
Physics

Refresh architecture and algorithm for non-volatile memories

#15 | 2012-12-04
US12764054
-

Multi-layer flash memory

#16 | 2012-11-29
US20120300546A1
Physics

Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells

#17 | 2012-11-15
US20120287698A1
Physics

Method for using a bit specific reference level to read a phase change memory

#18 | 2012-05-10
US20120113711A1
Physics

Using a bit specific reference level to read a memory

#19 | 2012-04-19
US20120092923A1
Physics

Read distribution management for phase change memory

#20 | 2011-07-21
US20110176358A1
Physics

Reading phase change memories

#21 | 2011-05-12
US20110113303A1
Physics

Method and apparatuses for customizable error correction of memory

#22 | 2010-11-11
US20100284212A1
Physics

Method for multilevel programming of phase change memory cells using adaptive reset pulses

#23 | 2010-07-01
US20100165719A1
Physics

Phase change memory device

#24 | 2009-05-07
US20090116281A1
Physics

Reading phase change memories

#25 | 2007-01-25
US20070019465A1
Physics

Detecting switching of access elements of phase change memory cells

#26 | 2006-10-12
US20060227592A1
Physics

Reading phase change memories

#27 | 2006-10-05
US20060221734A1
Physics

Detecting switching of access elements of phase change memory cells

#28 | 2006-03-09
US20060049392A1
Electricity

Process for manufacturing an array of cells including selection bipolar junction transistors

#29 | 2006-01-24
US10680721
-

Process for manufacturing an array of cells including selection bipolar junction transistors

#30 | 2005-08-04
US20050169095A1
Physics

Bit line discharge control method and circuit for a semiconductor memory

InventorID:

8032 ⎘