Vivek K. De

In-situ detection of anomalies in integrated circuits using machine learning models

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

ENERGY HARVESTING and AMBIENT CONDITION TRACKING in IoT for ADAPTIVE SENSING and SELF-MODIFYING APPLICATIONS

Energy harvester with multiple-input multiple-output switched-capacitor (MIMOSC) circuitry

Aging aware dynamic keeper apparatus and associated method

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Digitally controlled zero voltage switching

Digitally controlled zero current switching

Sequential circuit with error detection

Digital clamp for state retention

Apparatus for charge recovery during low power mode

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Resilient register file circuit for dynamic variation tolerance and method of operating the same

Link delay based routing apparatus for a network-on-chip

Apparatus and method for detecting or repairing minimum delay errors

POWER MANAGEMENT INTEGRATED CIRCUIT

Apparatus for reducing write minimum supply voltage for memory

Sequential circuit with error detection

Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode

Digitally phase locked low dropout regulator apparatus and system using ring oscillators

Apparatus for dual purpose charge pump

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode

Digital clamp for state retention

Sequential circuit with error detection

POWER MANAGEMENT INTEGRATED CIRCUIT

Resilient register file circuit for dynamic variation tolerance and method of operating the same

Apparatus for reducing write minimum supply voltage for memory

Circuits and methods for reducing minimum supply for register file cells

Multiphase transformer for a multiphase DC-DC converter

Circuits and methods for memory

Performing variation-aware profiling and dynamic core allocation for a many-core processor

Memory write operation methods and circuits

Power management integrated circuit

Component reliability budgeting system

CPU POWER DELIVERY SYSTEM

Method and apparatus for bus repeater tapering

Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode

MEMORY CIRCUIT WITH ECC BASED WRITEBACK

Component reliability budgeting system

Sense amplifier method and arrangement

Memory driver circuits with embedded level shifters

Power management integrated circuit

CMOS radiation-measuring circuit with a variable threshold

Bidirectional body bias regulation

Reliability degradation compensation using body bias

Statistical circuit design with carbon nanotubes

Majority voter circuit design

Component reliability budgeting system

Dual gate oxide one time programmable (OTP) antifuse cell

Memory cell having p-type pass device

Driver circuit

Leakage current reduction scheme for domino circuits

0th droop detector architecture and implementation

Capacitor structure for a logic process

Operating an information storage cell array

Memory circuit

Memory cell driver circuits

Apparatus and method for programming a memory array

Purge-based floating body memory

Memory with dynamically adjustable supply

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Reducing power consumption in integrated circuits

Apparatus for power consumption reduction

Method and apparatus to adjust die frequency

Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency

Signal measurement systems and methods

2-transistor floating-body dram

Representative majority voter for bus invert coding

Bias generator for body bias

Bias generator for body bias

Leakage current management

One time programmable memory

Body biasing methods and circuits

Body biasing for dynamic circuit

Memory circuit

Double gate transistor for low power circuits

Single-stage and multi-stage low power interconnect architectures

Method and apparatus to clamp SRAM supply voltage

CPU power delivery system

Floating-body dynamic random access memory with purge line

OTP antifuse cell and cell array

Processor apparatus with body bias circuitry to delay thermal throttling

Method and apparatus for measuring coil current

Power management integrated circuit

Non volatile data storage through dielectric breakdown

Crosspoint memory array utilizing one time programmable antifuse cells

Apparatus and method for a one-phase write to a one-transistor memory cell array

Floating-body memory cell write

SRAM cell power reduction circuit

Amplification gain stages having replica stages for DC bias control

System and method for applying within-die adaptive body bias

Frequency management apparatus, systems, and methods

Control circuitry in stacked silicon

Gating for dual edge-triggered clocking

Majority voter apparatus, systems, and methods

Charge storage memory cell

Memory cell without halo implant

Asymmetric memory cell

Method, apparatus and system of adjusting one or more performance-related parameters of a processor