Beaverton, Oregon
United States
36
2025-01-02
The entities that hold a legal rights for patent applications filed by inventor Le Van:
Van Le from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
N-TYPE TRANSISTOR FABRICATION IN COMPLEMENTARY FET (CFET) DEVICES
#2 | 2025-01-02AND DOUBLE PATTERNING STRATEGY WITH PRINTED ERASABLE DUMMIFICATION
#3 | 2024-10-03INTEGRATED CIRCUIT DEVICE WITH HETEROGENOUS TRANSISTORS
#4 | 2024-10-03CIRCUIT COMPONENTS WITH HIGH PERFORMANCE THIN FILM TRANSISTOR MATERIAL
#5 | 2024-09-26ARCHITECTURES AND METHODS FOR COMPUTATION IN MEMORY (CIM) WITH BACKSIDE MEMORY USING HIGH PERFORMANCE (HP) THIN FILM TRANSISTOR (TFT) MATERIAL
#6 | 2024-07-11PASSIVATION LAYERS FOR THIN FILM TRANSISTORS AND METHODS OF FABRICATION
#7 | 2024-03-28TRANSISTOR STRUCTURES WITH A METAL OXIDE CONTACT BUFFER AND A METHOD OF FABRICATING THE TRANSISTOR STRUCTURES
#8 | 2022-08-11Multi-die stacks with power management
#9 | 2022-02-17Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures
#10 | 2022-02-03Vias in composite IC chip structures
#11 | 2021-12-30Passivation layers for thin film transistors and methods of fabrication
#12 | 2021-12-30DOUBLE WALL CAPACITORS AND METHODS OF FABRICATION
#13 | 2021-12-02Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
#14 | 2021-09-30Computer-assisted or autonomous driving assisted by roadway navigation broadcast
#15 | 2021-04-01Packaged device with a chiplet comprising memory resources
#16 | 2021-04-01Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
#17 | 2021-04-01Vias in composite IC chip structures
#18 | 2020-12-31Transistor structures with a metal oxide contact buffer
#19 | 2020-12-31Vertical transistors for ultra-dense logic and memory applications
#20 | 2020-12-31Thin film transistors for memory cell array layer selection
#21 | 2019-12-12BANDGAP REFERENCE DIODE USING THIN FILM TRANSISTORS
#22 | 2019-11-21Self-aligned top-gated non-planar oxide semiconductor thin film transistors
#23 | 2019-10-03Thin film transistor with selectively doped oxide thin film
#24 | 2019-07-04Memory device with multiple memory arrays to facilitate in-memory computation
#25 | 2019-06-20Systems, methods and devices for isolation for subfin leakage
#26 | 2019-03-14MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY COMPUTATION
#27 | 2019-02-14Multi-die packages with efficient memory storage
#28 | 2019-02-14Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence
#29 | 2019-02-14Multi-die stacks with power management
#30 | 2019-02-14Computer-assisted or autonomous driving assisted by roadway navigation broadcast
#31 | 2018-09-06Local cell-level power gating switch
#32 | 2015-09-03Nanoscale structure with epitaxial film having a recessed bottom portion
#33 | 2014-06-26Defect transferred and lattice mismatched epitaxial film
#34 | 2014-06-26Lattice mismatched hetero-epitaxial film
#35 | 2014-06-26Epitaxial film on nanoscale structure
#36 | 2014-06-26Epitaxial film growth on patterned substrate
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