William C. Anderson

Register files for a digital signal processor operating in an interleaved multi-threaded environment

Large Ram Cache

Method and system for a digital signal processor debugging during power transitions

Embedded trace macrocell for enhanced digital signal processor debugging operations

Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor

Method and system for trusted/untrusted digital signal processor debugging operations

Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging

Power-efficient sign extension for booth multiplication methods and systems

Pointer computation method and system for a scalable, programmable circular buffer

Shared interrupt control method and system for a digital signal processor

Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor

System and method of controlling power in a multi-threaded processor

Shared translation look-aside buffer and method

System and method of executing program threads in a multi-threaded processor

Register files for a digital signal processor operating in an interleaved multi-threaded environment

Multi-mode instruction memory unit

System and method of using a predicate value to access a register file

Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment

Mixed superscalar and VLIW instruction issuing and processing method and system

Method and system for variable thread allocation and switching in a multithreaded processor

Method and system for encoding variable length packets with variable instruction sizes

Processor and method of indirect register read and write operations

Processor and method of grouping and executing dependent instructions in a packet

Digital signal processor computation core with input operand selection from operand bus for dual operations

Variable interleaved multithreaded processor method and system

Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism

Variable width alignment engine for aligning instructions based on transition between buffers

Use of a future file for data address calculations in a pipelined processor

Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation