Inventor profile of:

Olivier JOUBERT

City:

Meylan

Country:

France

Published Applications:

22

Last publication date:

2023-11-02

Top Assignees for applications by Olivier JOUBERT

The entities that hold a legal rights for patent applications filed by inventor JOUBERT Olivier:

Recent patent applications by JOUBERT Olivier

Olivier JOUBERT from Meylan, FR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-11-02
US20230352264A1
Electricity

Creating Ion Energy Distribution Functions (IEDF)

#2 | 2021-11-04
US20210343496A1
Electricity

Creating ion energy distribution functions (IEDF)

#3 | 2020-08-20
US20200266022A1
Electricity

Creating ion energy distribution functions (IEDF)

#4 | 2019-08-22
US20190259562A1
Electricity

Creating ion energy distribution functions (IEDF)

#5 | 2019-02-07
US20190043697A1
Electricity

MINIMIZATION OF RING EROSION DURING PLASMA PROCESSES

#6 | 2018-06-14
US20180166249A1
Electricity

Creating ion energy distribution functions (IEDF)

#7 | 2018-03-01
US20180057356A1
Performing operations; transporting

Wafer processing equipment having exposable sensing layers

#8 | 2017-10-26
US20170309497A1
Electricity

Method for manufacturing a resistive device for a memory or logic circuit

#9 | 2017-09-07
US20170256435A1
Electricity

Universal process kit

#10 | 2017-08-24
US20170243754A1
Electricity

Cyclic oxide spacer etch process

#11 | 2017-08-08
US15247717
Performing operations; transporting

Wafer processing equipment having exposable sensing layers

#12 | 2017-07-13
US20170200588A1
Electricity

Minimization of ring erosion during plasma processes

#13 | 2016-10-13
US20160300709A1
Electricity

Method for forming spacers for a transistor gate

#14 | 2016-02-04
US20160035581A1
Electricity

Microelectronic method for etching a layer

#15 | 2015-08-13
US20150228495A1
Electricity

Plasma etching process

#16 | 2014-11-13
US20140335695A1
Electricity

EXTERNAL UV LIGHT SOURCES TO MINIMIZE ASYMMETRIC RESIST PATTERN TRIMMING RATE FOR THREE DIMENSIONAL SEMICONDUCTOR CHIP MANUFACTURE

#17 | 2014-09-18
US20140273297A1
Electricity

Embedded test structure for trimming process control

#18 | 2014-09-18
US20140273292A1
Electricity

Methods of forming silicon nitride spacers

#19 | 2014-07-03
US20140187046A1
Electricity

METHOD FOR FORMING SPACERS FOR A TRANSITOR GATE

#20 | 2014-07-03
US20140187035A1
Electricity

Method of etching a porous dielectric material

#21 | 2014-07-03
US20140183159A1
Electricity

Method of obtaining patters in an antireflective layer

#22 | 2012-11-01
US20120276657A1
Electricity

Method of patterning of magnetic tunnel junctions

InventorID:

820156 ⎘