Inventor profile of:

Mattia ROBUSTELLI

City:

Milano

Country:

Italy

Published Applications:

29

Last publication date:

2026-04-23

Top Assignees for applications by Mattia ROBUSTELLI

The entities that hold a legal rights for patent applications filed by inventor ROBUSTELLI Mattia:

Recent patent applications by ROBUSTELLI Mattia

Mattia ROBUSTELLI from Milano, IT has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-23
US20260112411A1
Physics

READING A MULTI-LEVEL MEMORY CELL

#2 | 2025-11-06
US20250342889A1
Physics

UNIPOLAR PROGRAMMING OF MEMORY CELLS

#3 | 2025-08-28
US20250273272A1
Physics

APPARATUS WITH MULTI-BIT CELL READ MECHANISM AND METHODS FOR OPERATING THE SAME

#4 | 2025-08-14
US20250261380A1
Electricity

ASYMMETRIC MEMORY CELL DESIGN

#5 | 2025-07-10
US20250226029A1
Physics

CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS

#6 | 2025-04-10
US20250118372A1
Physics

WRITE LATENCY AND ENERGY USING ASYMMETRIC CELL DESIGN

#7 | 2024-12-26
US20240427699A1
Physics

REFERENCING MEMORY USING PORTIONS OF A SPLIT LOGICAL BLOCK ADDRESS

#8 | 2024-12-05
US20240404590A1
Physics

TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING

#9 | 2024-11-21
US20240386963A1
Physics

Programming techniques for polarity-based memory cells

#10 | 2024-09-26
US20240321347A1
Physics

READING A MULTI-LEVEL MEMORY CELL

#11 | 2024-07-11
US20240233828A9
Physics

APPARATUS WITH MULTI-BIT CELL READ MECHANISM AND METHODS FOR OPERATING THE SAME

#12 | 2024-07-04
US20240221829A1
Physics

Cross-point pillar architecture for memory arrays

#13 | 2024-04-25
US20240135996A1
Physics

Apparatus with multi-bit cell read mechanism and methods for operating the same

#14 | 2024-02-08
US20240049610A1
Electricity

DOPANT-MODULATED ETCHING FOR MEMORY DEVICES

#15 | 2024-01-25
US20240029796A1
Physics

UNIPOLAR PROGRAMMING OF MEMORY CELLS

#16 | 2023-11-09
US20230360699A1
Physics

Techniques for multi-level chalcogenide memory cell programming

#17 | 2023-11-02
US20230354619A1
Electricity

Asymmetric memory cell design

#18 | 2023-11-02
US20230352095A1
Physics

Write latency and energy using asymmetric cell design

#19 | 2023-06-29
US20230207002A1
Physics

Cross-point pillar architecture for memory arrays

#20 | 2023-02-02
US20230034787A1
Physics

Programming techniques for polarity-based memory cells

#21 | 2022-09-22
US20220301619A1
Physics

Reading a multi-level memory cell

#22 | 2022-04-21
US20220122664A1
Physics

Programming memory cells using asymmetric current pulses

#23 | 2022-03-03
US20220068391A1
Physics

Programming techniques for polarity-based memory cells

#24 | 2022-01-13
US20220013167A1
Physics

Reading a multi-level memory cell

#25 | 2020-09-03
US20200279604A1
Physics

Dedicated read voltages for data structures

#26 | 2020-05-07
US20200143880A1
Physics

Dedicated read voltages for data structures

#27 | 2017-08-24
US20170243643A1
Physics

Phase change memory devices and systems having reduced voltage threshold drift and associated methods

#28 | 2014-07-03
US20140185387A1
Physics

Semiconductor memory device and method of operating the same

#29 | 2011-10-13
US20110249501A1
Physics

Dynamic polarization for reducing stress induced leakage current

InventorID:

822407 ⎘