Inventor profile of:

Niranjan Cooray

City:

Folsom, California

Country:

United States

Published Applications:

24

Last publication date:

2025-12-11

Top Assignees for applications by Niranjan Cooray

The entities that hold a legal rights for patent applications filed by inventor Cooray Niranjan:

Recent patent applications by Cooray Niranjan

Niranjan Cooray from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-12-11
US20250378045A1
Physics

DYNAMIC MEMORY RECONFIGURATION

#2 | 2025-06-26
US20250209021A1
Physics

SCALABLE I/O VIRTUALIZATION INTERRUPT AND SCHEDULING

#3 | 2025-05-29
US20250173308A1
Physics

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

#4 | 2024-09-26
US20240320184A1
Physics

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

#5 | 2024-08-01
US20240256483A1
Physics

Graphics processor data access and sharing

#6 | 2024-06-06
US20240184739A1
Physics

DYNAMIC MEMORY RECONFIGURATION

#7 | 2024-03-21
US20240095201A1
Physics

Scalable I/O virtualization interrupt and scheduling

#8 | 2023-09-28
US20230306551A1
Physics

COMPRESSION USING A FLAT MAPPING IN VIRTUAL ADDRESS SPACE

#9 | 2023-09-21
US20230298129A1
Physics

LOCAL MEMORY TRANSLATION TABLE ACCESSED AND DIRTY FLAGS

#10 | 2023-09-21
US20230298128A1
Physics

LOCAL MEMORY TRANSLATION TABLE

#11 | 2023-09-21
US20230297526A1
Physics

Scalable I/O virtualization interrupt and scheduling

#12 | 2022-05-05
US20220137967A1
Physics

Assistance for hardware prefetch in cache access

#13 | 2022-04-07
US20220107914A1
Physics

Multi-tile architecture for graphics operations

#14 | 2022-03-03
US20220066931A1
Physics

Dynamic memory reconfiguration

#15 | 2021-08-19
US20210255951A1
Physics

Memory compression hashing mechanism

#16 | 2020-09-24
US20200301826A1
Physics

Memory compression hashing mechanism

#17 | 2020-01-02
US20200004683A1
Physics

Cache partitioning mechanism

#18 | 2019-10-24
US20190324919A1
Physics

Page tables for granular allocation of memory pages

#19 | 2019-07-11
US20190213707A1
Physics

Scalable memory interface for graphical processor unit

#20 | 2019-05-30
US20190163641A1
Physics

PAGE TRANSLATION PREFETCH MECHANISM

#21 | 2019-05-16
US20190146714A1
Physics

Surface property tracking mechanism

#22 | 2015-08-06
US20150220436A1
Physics

Power efficient level one data cache access with pre-validated tags

#23 | 2014-07-03
US20140189250A1
Physics

Store forwarding for data caches

#24 | 2007-06-28
US20070150653A1
Physics

Processing of cacheable streaming data

InventorID:

827157 ⎘