Brent Bean

Branch density detection for prefetcher

Processor with instruction cache that performs zero clock retires

Processor with instruction cache that performs zero clock retires

System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions

System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction

System and method of determining memory ownership on cache line basis for detecting self-modifying code

System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries

Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state

Microprocessor using compressed and uncompressed microcode storage

Key expansion logic using decryption key primitives

Microprocessor with on-the-fly switching of decryption keys

Microprocessor with secure execution mode and store key instructions

Decryption of encrypted instructions using keys selected on basis of instruction fetch address

Selectively compressed microcode

Microprocessor with compressed and uncompressed microcode memories

Single core wakeup multi-core synchronization mechanism

Uncore microcode ROM

Microprocessor that facilitates task switching between encrypted and unencrypted programs

Microprocessor that securely decrypts and executes encrypted instructions

Method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program

Apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor

U-SHAPED SHELF

Microprocessor that fetches and decrypts encrypted instructions in same time as plain text instructions

Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions

Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key values

Microprocessor that facilitates task switching between encrypted and unencrypted programs

Branch and switch key instruction in a microprocessor that fetches and decrypts encrypted instructions

Switch key instruction in a microprocessor that fetches and decrypts encrypted instructions

Out-of-order microprocessor with separate branch information circular queue table tagged by branch instructions in reorder buffer to reduce unnecessary space in buffer

Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor

Microprocessor with fast execution of call and return instructions

Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state

Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution

Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state

Pipelined microprocessor with fast conditional branch instructions based on static exception state

Pipelined microprocessor with normal and fast conditional branch instructions

Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution

PERFORMANCE COUNTER FOR MICROCODE INSTRUCTION EXECUTION

Out-of-order execution microprocessor that selectively initiates instruction retirement early

Apparatus and method for handling BTAC branches that wrap across instruction cache lines

Apparatus and method for handling BTAC branches that wrap across instruction cache lines