Lee WANG

FAST MOSFET DEVICE THRESHOLD VOLTAGE SENSING SCHEME FOR SEMICONDUCTOR NON-VOLATILE MEMORY

GRADED CHANNEL DEVICES FOR NOR FLASH CELL ARRAY AND METHOD OF FABRICATING THE SAME

FOUR-TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL WITH ENHANCED DATA RETENTION

BINARY FLOATING-POINT IN-MEMORY MULTIPLICATION DEVICE

NEURON METAL OXIDE SEMICONDUCTOR DEVICES AND CIRCUITS FABRICATED WITH CMOS LOGIC PROCESS TECHNOLOGY

OPERATION SCHEME FOR FOUR TRANSISTOR STATIC RANDOM ACCESS MEMORY

Methods of erasing semiconductor non-volatile memories

Multiple-digit binary in-memory multiplier devices

Extendable multiple-digit base-2in-memory adder device

Perpectual digital perceptron

Dynamic digital perceptron

In-memory arithmetic processors

Configurable non-volatile arithmetic memory operators

Methods of erasing semiconductor non-volatile memories

Digital neuromorphic code processor

Memory cell size reduction for scalable logic gate non-volatile memory arrays

MOSFET threshold voltage sensing scheme for non-volatile memory

Standby current reduction in digital circuitries

Digital perceptron

Recess channel semiconductor non-volatile memory device and fabricating the same

Configurable non-volatile content addressable memory

Configurable non-volatile content addressable memory

NON-VOLATILE REGISTER AND NON-VOLATILE SHIFT REGISTER

Ultra-low power programming method for N-channel semiconductor non-volatile memory

Multiple-time configurable non-volatile look-up-table

Non-volatile register and non-volatile shift register

Interconnection matrix using semiconductor non-volatile memory

3-D single floating gate non-volatile memory device

Structures and operational methods of non-volatile dynamic random access memory devices

Complementary electrical erasable programmable read only memory

Structures and methods of high efficient bit conversion for multi-level cell non-volatile memories

Dual conducting floating spacer metal oxide semiconductor field effect transistor (DCFS MOSFET) and method to fabricate the same

Scalable gate logic non-volatile memory cells and arrays

Method for fabricating a field side sub-bitline nor flash array

Non-volatile static random access memory devices and methods of operations

Field side sub-bitline nor flash array and method of fabricating the same

Structures and methods for reading out non-volatile memories

Dual conducting floating spacer metal oxide semiconductor field effect transistor (DCFS MOSFET) and method to fabricate the same

Methods and structures for reading out non-volatile memory using NVM cells as a load element

Methods and structures for reading out non-volatile memory using NVM cells as a load element

Level verification and adjustment for multi-level cell (MLC) non-volatile memory (NVM)

Structures and methods to store information representable by a multiple-bit binary word in electrically erasable, programmable read-only memory (EEPROM)

Level verification and adjustment for multi-level cell (MLC) non-volatile memory (NVM)

Structures and methods to store information representable by a multiple bit binary word in electrically erasable, programmable read-only memories (EEPROM)

Method and structures for highly efficient hot carrier injection programming for non-volatile memories

Bit-symbol recognition method and structure for multiple-bit storage in non-volatile memories

Self-adaptive and self-calibrated multiple-level non-volatile memories

Bit symbol recognition method and structure for multiple bit storage in non-volatile memories

High-speed low-voltage programming and self-convergent high-speed low-voltage erasing schemes for EEPROM