GEORGETOWN, Texas
United States
31
2018-05-17
The entities that hold a legal rights for patent applications filed by inventor FLACHS BRIAN:
BRIAN FLACHS from GEORGETOWN, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Arranging binary code based on call graph partitioning
#2 | 2017-06-08Arranging binary code based on call graph partitioning
#3 | 2017-01-12Arranging binary code based on call graph partitioning
#4 | 2016-04-28Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory
#5 | 2014-09-04Selection of post-request action based on combined response and input from the request source
#6 | 2014-09-04Selection of post-request action based on combined response and input from the request source
#7 | 2012-08-09Rewriting branch instructions using branch stubs
#8 | 2012-08-02Arranging binary code based on call graph partitioning
#9 | 2012-08-02Dynamically rewriting branch instructions in response to cache line eviction
#10 | 2012-08-02Dynamically rewriting branch instructions to directly target an instruction cache location
#11 | 2012-05-03Secure Page Tables in Multiprocessor Environments
#12 | 2012-03-08Arithmetic decoding acceleration
#13 | 2012-01-26Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set
#14 | 2011-12-29Arranging binary code based on call graph partitioning
#15 | 2011-12-29Rewriting branch instructions using branch stubs
#16 | 2011-12-29Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction
#17 | 2011-12-29Dynamically rewriting branch instructions to directly target an instruction cache location
#18 | 2011-06-16Optimization of software instruction cache by line re-ordering
#19 | 2009-08-13System for limiting the size of a local storage of a processor
#20 | 2009-03-12Design Structure For A Processor System With Background Error Handling Feature
#21 | 2008-12-11Method and apparatus for cooperative software multitasking in a processor system with a partitioned register file
#22 | 2008-11-04System and method for sorting processors based on thermal design point
#23 | 2008-08-07System and Method for Determining a Guard Band for an Operating Voltage of an Integrated Circuit Device
#24 | 2008-05-29Middlesoft commander
#25 | 2008-05-29STIMULATING AND RECEIVING TEST/DEBUG DATA FROM A SYSTEM UNDER TEST VIA A DRONE CARD PCI BUS
#26 | 2008-05-01Method and apparatus for testing to determine minimum operating voltages in electronic devices
#27 | 2008-04-17Optimizing a Set of LBIST Patterns to Enhance Delay Fault Coverage
#28 | 2008-04-03Modifying a test pattern to control power supply noise
#29 | 2007-08-09Processor system and methodology with background error handling feature
#30 | 2007-04-10Impedane measurement of chip, package, and board power supply system using pseudo impulse response
#31 | 2007-02-22Method for limiting the size of a local storage of a processor
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