Inventor profile of:

Lu Fei

City:

St. Louis, Missouri

Country:

United States

Published Applications:

12

Last publication date:

2019-05-09

Top Assignees for applications by Lu Fei

The entities that hold a legal rights for patent applications filed by inventor Fei Lu:

Recent patent applications by Fei Lu

Lu Fei from St. Louis, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-05-09
US20190139818A1
Electricity

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

#2 | 2017-11-02
US20170316968A1
Electricity

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

#3 | 2014-11-06
US20140327112A1
Electricity

Method to delineate crystal related defects

#4 | 2012-09-20
US20120238070A1
Electricity

Methods for producing silicon on insulator structures having high resistivity regions in the handle wafer

#5 | 2012-09-20
US20120235283A1
Electricity

SILICON ON INSULATOR STRUCTURES HAVING HIGH RESISTIVITY REGIONS IN THE HANDLE WAFER

#6 | 2012-05-10
US20120115258A1
Electricity

Methods for monitoring the amount of metal contamination in a process

#7 | 2011-09-01
US20110212550A1
Electricity

METHODS FOR DETECTING METAL PRECIPITATES IN A SEMICONDUCTOR WAFER

#8 | 2011-09-01
US20110212547A1
Electricity

METHODS FOR MONITORING THE AMOUNT OF METAL CONTAMINATION IMPARTED INTO WAFERS DURING A SEMICONDUCTOR PROCESS

#9 | 2011-08-25
US20110207246A1
Electricity

Methods for reducing the width of the unbonded region in SOI structures

#10 | 2011-08-25
US20110204471A1
Electricity

Semiconductor wafers with reduced roll-off and bonded and unbonded SOI structures produced from same

#11 | 2011-06-23
US20110151592A1
Electricity

Methods for monitoring the amount of contamination imparted into semiconductor wafers during wafer processing

#12 | 2006-08-29
US10441413
-

Single crystal silicon wafer having an epitaxial layer substantially free from grown-in defects

InventorID:

958720 ⎘