Interleaved encoding

Description

BACKGROUND OF THE INVENTION

Multi-dimensional codes are widely used due to their potential efficiency. In NAND flash memory systems the reliability requirement dictates operation in extremely low output bit error rate (BER), for example, this can be output BER that is below ten by the power of minus fifteen.

For achieving such goal, the encoding system should have a very low error-floor. There are various methods of designing codes and decoder for low error floor. Novel methods for encoding and decoding for obtaining low-error-floor codes are suggested in this application.

SUMMARY

According to an embodiment of the invention there may be provided a method for interleaved multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits; and encoding, by an encoder, the first and second versions of the groups of bits in an interleaved manner; wherein the encoding may include calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version and calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.

The encoding may include calculating a minority of codeword components of the first version in response to at least portions of data entities of the second version and calculating a majority of codeword components of the first version regardless of the at least portions of data entities of the second version.

The encoding may include calculating a majority of codeword components of the first version in response to at least portions of data entities of the second version and calculating a minority of codeword components of the first version regardless of the at least portions of data entities of the second version.

The at least a portion of a redundancy of a certain data entity of the second version may affect a calculation of only a single codeword component of the first version.

The method may include calculating a certain codeword component of a version of the first and second versions without taking into account a redundancy of another codeword of another version of the first and second versions.

The at least a portion of a redundancy of a certain data entity of the second version may affect a calculation of multiple codeword components of the first version.

The one or more codeword components of the first version may differ by length from one or more codeword components of the second version.

The two or more codeword components of a same version out of the first and second versions may differ by length from each other.

The encoding may include calculating a first codeword component by encoding a first data entity that belongs to of the first version; calculating a second codeword component by encoding, before a completion of an encoding of the first version, a second data entity that belongs to the second version and at least a portion of the first codeword component; calculating a third codeword component by encoding a third data entity that belongs to the first version and at least a portion of the second codeword component; calculating a fourth codeword component by encoding a fourth data entity that belongs to the second version and at least a portion of the third codeword component.

The at least portion of the second codeword component may include one or more second codeword component redundancy bits.

The encoding may include calculating a first codeword component by encoding a first data entity that belongs to of the first version; calculating a second codeword component by encoding a second data entity that belongs to of the second version; calculating a third codeword component by encoding, before a completion of an encoding of the first version, a third data entity that belongs to the first version and at least a portion of the second codeword component; calculating a fourth codeword component by encoding a fourth data entity that belong to the second version and at least a portion of the first codeword component.

The multi-dimensional encoding may include encoding multiple (K) versions of the group of bits that correspond to K dimensions; wherein the method further may include jointly encoding portions of redundancies of a K'th dimension and portions of redundancies of a lower than K dimension to provide joint redundancy.

The joint redundancy may include multiple joint redundancy units, wherein at least one joint redundancy unit is generated by encoding at least a portion of a K'th dimension redundancy unit and at least a portion of a (K−q)'th redundancy portion, q being a positive integer that ranges between 1 and (K−1).

According to an embodiment of the invention there may be provided a method for multi-dimensional encoding, the method may include encoding, by an encoder, multiple versions of a group of bits that correspond to multiple dimensions; and jointly encoding portions of redundancies of a last dimension of the multiple dimensions and portions of redundancies of a not-last dimension to provide joint redundancy.

The joint redundancy may include multiple joint redundancy units, wherein at least one joint redundancy unit is generated by encoding at least a portion of a last dimension redundancy unit and at least a portion of the non-last redundancy portion.

According to an embodiment of the invention there may be provided a method for decoding an interleaved multi-dimensional codeword, the method may include receiving a multi-dimensional codeword that was encoded in an interleaved manner; and decoding, by a decoder, the multi-dimensional codeword; wherein the multi-dimensional codeword was calculated by receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits; an encoding the first and second versions of the groups of bits in the interleaved manner; wherein the encoding may include calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version and calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.

According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to perform the stages of receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits; and encoding the first and second versions of the groups of bits in an interleaved manner; wherein the encoding may include calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version and calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.

According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to perform the stages of encoding multiple versions of a group of bits that correspond to multiple dimensions; and jointly encoding portions of redundancies of a last dimension of the multiple dimensions and portions of redundancies of a not-last dimension to provide joint redundancy

According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to perform the stages of receiving a multi-dimensional codeword that was encoded in an interleaved manner; and decoding the multi-dimensional codeword; wherein the multi-dimensional codeword was calculated by receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits; an encoding the first and second versions of the groups of bits in the interleaved manner; wherein the encoding may include calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version and calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.

According to an embodiment of the invention there may be provided a system that may include an encoder; wherein the system is arranged to receive or generate a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits; and wherein the encoder is arranged to encode the first and second versions of the groups of bits in an interleaved manner; wherein the encoding may include calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version and calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.

According to an embodiment of the invention there may be provided a system that may include an encoder; wherein the encoder is arranged to encode, multiple versions of a group of bits that correspond to multiple dimensions; and jointly encoding portions of redundancies of a last dimension of the multiple dimensions and portions of redundancies of a not-last dimension to provide joint redundancy

According to an embodiment of the invention there may be provided a system that may include an decoder; wherein the system is arranged to receive a multi-dimensional codeword that was encoded in an interleaved manner; wherein the decoder is arranged to decode, the multi-dimensional codeword; wherein the multi-dimensional codeword was calculated by receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits; an encoding the first and second versions of the groups of bits in the interleaved manner; wherein the encoding may include calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version and calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

FIG. 1 illustrates a method according to an embodiment of the invention;

FIGS. 2-5 illustrate codewords according to various embodiments of the invention;

FIG. 6 illustrates a system that includes two dimensional encoder with folded redundancy encoding according to an embodiment of the invention;

FIG. 7 illustrates a method according to an embodiment of the invention;

FIGS. 8-10 illustrate a two dimensional codeword according to various embodiments of the invention; and

FIG. 11 illustrates a flow chart according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that once executed by a computer result in the execution of the method.

Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that may be executed by the system.

Any reference in the specification to a non-transitory computer readable medium should be applied mutatis mutandis to a system capable of executing the instructions stored in the non-transitory computer readable medium and should be applied mutatis mutandis to method that may be executed by a computer that reads the instructions stored in the non-transitory computer readable medium.

Multi-dimensional encoding invoices receiving or generating multiple versions of a group of bits. The different versions differ from each other by the arrangement of bits. Different versions are associated with different dimensions. For example—assuming that that there are two dimensions and that the bits of the group of bits are arranged in a virtual (rectangular) matrix. According to a first arrangement of the bits, (first dimension) payloads are formed by the rows of the matrix. According to a second arrangement of the bits (second dimension) payloads are formed by the columns of the matrix. In a non-folded arrangement each payload occupies a single row or column. In a folded arrangement a single payload (of a single codeword component) can occupy more than a single row or column.

Various examples of multi-dimensional encoding are provided in U.S. Pat. Nos. 8,700,970, 8,341,502, 8,621,321, 8,510,639, 8,468,431, and US patent application 20130132793, all being incorporated herein by reference.

Prior art multi-dimensional encoding included serial concatenation, where a dimension is encoded only after the other dimension was entirely encoded. This way, the redundancy of one dimension is protected by the other dimension. However, the last dimension may be unprotected. Another prior art (3D application) the each dimension encoding generates a redundancy for codeword components of its dimension, the resulting overall redundancy may then be encoded with another encoder. This type of encoding is not too efficient as the redundancy is protected due to an additional code, and does not take part in the encoding process (like suggested in this invention).

According to an embodiment of the invention there is provided an interleaved multi-dimensional encoding scheme in which one or more encoding results of a first dimension affect one or more encoding results of a second dimension and one or more encoding results of the second dimension affect one or more encoding results of the first dimension. The interleaving can be applied on one, some, part or all group of bits of either one of the first and second dimensions. The interleaving may require that the encoding of a dimension out of the first and second dimensions is not completed before starting the encoding of the other dimension.

In the following examples it is assumed that there are two dimensions and that the bits are arranged in a two dimensional matrix. These are only non-limiting assumptions. There may be K dimensions and K may exceed 2. The bits may be arranged in different manners and the matrix is merely provided to simplify the explanation.

FIG. 1 illustrates method 300 according to an embodiment of the invention.

Method 300 may start by stage 310 of receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits.

One (or none) of the first and second versions may be the data unit. One or both first and second versions may differ from the data unit. One or both of the first and second versions of the data unit may be generated by interleaving.

The first and second versions are associated with first and second dimensions of the multi-dimensional encoding. Thus, encoding the first version may be referred to as first dimension encoding and encoding the second version may be referred to as second dimension encoding.

Stage 310 may be followed by stage 320 of encoding the first and second versions of the groups of bits in an interleaved manner.

Stage 320 may include stages 311, 322 and 324.

Stage 311 may include calculating a certain codeword component of a version (of the first and second versions) without taking into account a redundancy of another codeword of another version (of the first and second versions). For example—the first encoding of the first codeword component of the first or second version can be performed on a payload that may include only data.

Stage 322 may include calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version.

Stage 324 may include calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.

Stages 322 and 324 may be executed for encoding a minority, a half, a majority of codeword components of the first version while the remaining (if such exist) codeword components can be calculated regardless of the at least portions of data entities of the second version.

FIGS. 2-4 illustrate a two-dimensional codeword 10 (and 200) that includes row payloads P11-P18 11-18, each extending over more than a single row. First row payload P11 11 includes only bits of a first version of a data unit. Other row payloads P12-P18 include bits of a first version of the data unit as well as redundancy bits of column codeword components. For example, row payloads P12 and P13 include bits of redundancy R21 121. Every codeword component can be for example a short BCH (Bose-Chaudhuri-Hocquenghem) code, or a Hamming code, or any other short block code.

The two-dimensional codeword 10 includes column payloads P21-P29 21-29, each extending over more than a single column. First column payload P21 21 includes only bits of a second version of the data unit. Other column payloads P22-P29 include bits of a second version of the data unit as well as redundancy bits of row codeword components. For example, row payloads P22 and P23 include bits of redundancy R11 111.

Because of the interleaved encoding, the redundancy bits (and the codeword components) are calculated in a serial manner. At any point of time, the redundancy of a codeword component can be calculated if all bits of the payload are available. When some bits are still unknown (for example—are redundancy bits that are not calculated yet) the calculation of the codeword component should be postponed.

This serial nature of the interleaving process is illustrated in FIG. 4. In this figure, gaps are left for redundancy bits that are not calculated yet.

The top part of FIG. 4 illustrates two calculated redundancies R11 111 and R21 121 while other redundancy bits are not calculated yet and there are gaps 150 at the locations of such redundancies.

The lower part of FIG. 4 illustrates four calculated redundancies R11 111, R21 121, R12 112, and R22 122 while other redundancy bits are not calculated yet and there are gaps 150 at the locations of such redundancies. R12 112 and R22 122 can be calculated only after R11 111 and R21 121 are calculated. The arrows demonstrate what part of the payload is used for generating R11 111 and R21 121 in the upper part of the figure, and then R12 112 and R22 122 on the lower part of FIG. 4.

It is noted that the number of row codeword components that can be affected by a redundancy of a single column component code can be one or more. The number of column codeword components that can be affected by a redundancy of a single row component code can be one or more. The payload length for every codeword component may also be different per codeword. A first example of a relationship between row and column component codes are illustrated in FIGS. 2-4. Another example is illustrated in FIG. 5.

It is noted that the interleaved encoding can include jumping between versions after encoding a single payload or after encoding multiple payloads. FIGS. 2-4 illustrated an encoding of a single payload per each version—before jumping to the calculation of the next two codewords. In this case the execution of stage 320 may include:

• • a. Calculating a first codeword component by encoding a first data entity that belongs to of the first version. For example—calculating R11 111.
  • b. Calculating a second codeword component by encoding a second data entity that belongs to of the second version. For example—calculating R21 121.
  • c. Calculating a third codeword component by encoding, before a completion of an encoding of the first version, a third data entity that belongs to the first version and at least a portion of the second codeword component. For example—calculating R12 121.
  • d. Calculating a fourth codeword component by encoding a fourth data entity that belongs to the second version and at least a portion of the first codeword component. For example—calculating R22 122.

Yet for another example—these stages may include calculating a first codeword component by encoding a first data entity that belongs to the first version; calculating a second codeword component by encoding, before a completion of an encoding of the first version, a second data entity that belongs to the second version and at least a portion of the first codeword component; calculating a third codeword component by encoding a third data entity that belongs to the first version and at least a portion of the second codeword component and calculating a fourth codeword component by encoding a fourth data entity that belongs to the second version and at least a portion of the third codeword component.

According to an embodiment of the invention, the interleaved encoding may be applied to protect redundancies.

In this case, stage 320 may be used for encoding multiple (K) versions of the group of bits that correspond to K dimensions.

Stage 320 may be followed by stage 330 of jointly encoding portions of redundancies of a K'th dimension and portions of redundancies of a lower than K dimension to provide joint redundancy.

The joint redundancy includes multiple joint redundancy units. At least one joint redundancy unit is generated by encoding at least a portion of a K'th dimension redundancy unit and at least a portion of a (K−q)'th redundancy portion, q being a positive integer that ranges between 1 and (K−1).

FIG. 6 illustrates a system that includes a two dimensional encoder 8 with folded redundancy encoding according to an embodiment of the invention.

The two dimensional encoder 8 may be included in a memory controller 9 that is coupled to a memory module 9′ such as a flash memory module. Memory controller 9 may also include an encoder 8′. FIG. 6 illustrates an encoder 8 that outputs a codeword. It may output one or more codeword component of the codeword.

Once a codeword component encoding is completely encoded (encoded codeword is ready, i.e. its redundancy is fully computed), its redundancy is passed to the encoders of the other dimension, and it is taken as additional input data to encoders of the other dimension. Consider for example, K-input bits, which pass through interleaver D0 1 on the first dimension, and through interleaver D1 2 of the other dimension. D0 has multiple encoders (D0 encoders 3) (which in a special case may be identical); each encoder receives a different portion of the D0-interleaved input bits.

D0 encoders 3 begin by encoding packets, which do not need D1-redundancy bits for encoding completion (the minimum is a single packet). Then each time D0 encoders 3 completed the encoding of a packet, it passes the associated redundancy bits through its D0-Redundancy-interleaver 5 to D1 encoders (D1 encoders 4), which use this input for jointly encoding the input data and the input redundancy, at the same time. The same applies to the D1 encoders 4-D1 encoders 4 begins by encoding packets which do not need D0-redundancy bits for encoding completion (the minimum is a single packet). Then each time D1 encoders 4 completed the encoding of a packet, it passes the encoded redundancy bits through its D1-Redundancy-interleaver 6 to D0 encoders (D0 encoders 3), which use this input for jointly encoding the input data and the input redundancy, at the same time.

That is, both D0 and D1 encoders 3 and 4 may operate in parallel (or in a serial manner) in order to provide intermittent results and enable protecting most of the redundancy bits generated by code components with codes on other dimensions. Naturally, the last code component on each dimension will not have an encoded redundancy, since it encodes the last portion of the input bits to the encoder. Therefore, the last few component codes may (optionally) have an additional D2-encoder, which encodes the less protected parity bits. Thus, the systematic codeword consists of K-input bits, D0-Redundancy, D1-Redundancy, and D2-Redundancy.

According to an embodiment of this invention, every codeword component can be of a different code rate. This creates an irregular folded BCH code, and may be used instead of having the D2-encoder. Methods for obtaining different code component strengths include for example, using varying length per component encoder, while using the same BCH parameters (field size—Q, and number of errors—t).

FIG. 7 illustrates a method 400 for multi-dimensional encoding, according to an embodiment of the invention.

Method 400 may start by stage 410 of encoding multiple versions of a group of bits that correspond to multiple dimensions. Stage 410 may include any stage of method 300. Other encoding schemes may be used.

Stage 410 may be followed by stage 420 of jointly encoding portions of redundancies of a last dimension of the multiple dimensions and portions of redundancies of a not-last dimension to provide joint redundancy.

The joint redundancy may include multiple joint redundancy units, wherein at least one joint redundancy unit is generated by encoding at least a portion of a last dimension redundancy unit and at least a portion of the non-last redundancy portion.

FIGS. 8-10 illustrates two dimensional codeword 200 according to various embodiments of the invention. It includes row payloads D1,1-D1,12 210(1,1)-210(1,12) that occupy one row each and include only data bits. It also includes column payloads D2,1-D2,12 220(1,1)-220(1,12) that occupy one row each and include only data bits.

The row payloads (first dimension, first version) were encoded to provide row redundancies R1,1-R1,12 230(1,1)-230(1,12).

The column payloads (second dimension, second version) were encoded to provide column redundancies R2,1-R2,12 240(2,1)-240(2,12).

FIG. 8 illustrates a first joint redundancy R3 250 that includes first joint redundancy units, each is calculated by encoding a single row redundancy and multiple bits from multiple column redundancies. For example first joint redundancy unit 251 is calculated by encoding R1,3 230(1,3) and multiple bits (241) from multiple column redundancies.

FIG. 9 illustrates a second joint redundancy R4 260 that includes first joint redundancy units, each is calculated by encoding a single column redundancy and multiple bits from multiple row redundancies. For example second joint redundancy unit 261 is calculated by encoding R2,7 240(2,7) and multiple bits (231) from multiple row redundancies.

FIG. 10 illustrates a first joint redundancy R3 250 that includes first joint redundancy units, each is calculated by encoding a multiple bits from multiple column redundancies and multiple bits from multiple column redundancies. For example second joint redundancy unit 252 is calculated by encoding multiple bits (231) from row redundancies and multiple bits (241) from multiple column redundancies. For simplicity of explanation, the arrows connecting the multiple bits (241, 231) to second joint redundancy unit 252 were omitted. FIG. 10 also includes second joint redundancy 260.

It is noted that only one of the first and second joint redundancies can be provided, that the encoding can be applied to more than two dimensions, and that the encoding may be responsive to the data bits and not just to the redundancies.

It is noted that the decoding process may be done in various manners. The decoding can also be iterative decoding. Non-limiting examples of decoding include:

• • a. Iterative irregular multi-dimensional decoding (using codeword components of different size and/or different rate).
  • b. Using soft decoding with list decoding.
  • c. Applying hard and/or soft decoding with false correction elimination (FCE) methods.
  • d. Performing hard decoding with intersections decoding.

The invention may also be implemented in a computer program for running on a computer system, at least including code portions for performing steps of a method according to the invention when run on a programmable apparatus, such as a computer system or enabling a programmable apparatus to perform functions of a device or system according to the invention. The computer program may cause the storage system to allocate disk drives to disk drive groups.

A computer program is a list of instructions such as a particular application program and/or an operating system. The computer program may for instance include one or more of a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library, and/or other sequence of instructions designed for execution on a computer system.

The computer program may be stored internally on a non-transitory computer readable medium. All or some of the computer program may be provided on computer readable media permanently, removably or remotely coupled to an information processing system. The computer readable media may include, for example and without limitation, any number of the following magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.

A computer process typically includes an executing (running) program or portion of a program, current program values and state information, and the resources used by the operating system to manage the execution of the process. An operating system (OS) is the software that manages the sharing of the resources of a computer and provides programmers with an interface used to access those resources. An operating system processes system data and user input, and responds by allocating and managing tasks and internal system resources as a service to users and programs of the system.

The computer system may for instance include at least one processing unit, associated memory and a number of input/output (I/O) devices. When executing the computer program, the computer system processes information according to the computer program and produces resultant output information via I/O devices.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. In addition, plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.

Although specific conductivity types or polarity of potentials have been described in the examples, it will be appreciated that conductivity types and polarities of potentials may be reversed.

Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein may be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

Furthermore, the terms “assert” or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. Moreover, if the logically true state is a logic level zero, the logically false state is a logic level one.

Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.

Also for example, the examples, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type.

Also, the invention is not limited to physical devices or units implemented in non-programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code, such as mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices, commonly denoted in this application as ‘computer systems’.

However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.