Parallel encoding method and system

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to co-pending U.S. patent application Ser. No. 14/323,857, entitled “Interleaved Encoding” by Hanan Weingarten and Avi Steiner, owned by the assignee of this application and incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

Multi-dimensional codes are widely used due to their potential efficiency. In NAND flash memory systems the reliability requirement dictates operation in extremely low output bit error rate (BER), for example, this can be output BER that is below ten by the power of minus fifteen.

For achieving such goal the encoding system should have a very low error-floor. There are various methods of designing codes and decoder for low error floor. Novel methods for encoding and decoding for obtaining low-error-floor codes are suggested in this application.

SUMMARY

According to an embodiment of the invention there may be provided a method for parallel multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; selecting a first set of bits of the first version and a second set of bits of the second version; encoding, in parallel, the first set of bits and the second set of bits; wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits; and wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.

The first set of bits may be a part of the first version and the second set of bits may be a part of the second version.

The first set of bits may equal the first version and the second set of bits may equal the second version.

At least one of the first set of bits and the second set of bits may include data bits and does not include redundancy bits.

At least one of the first set of bits and the second set of bits may not include data bits and may include redundancy bits.

Each one of the first set of bits and the second set of bits may not include data bits and may include redundancy bits.

The encoding of the second set of bits may be executed by applying an encoding process that is associated with the second set of bits.

At least one of the first and second versions may be an interleaved version of the group of bits.

The method may include selecting and the encoding until all first sets of bits of the first version are selected and encoded.

The method may include repeating the selecting and the encoding until only a part of all first sets of bits of the first version are selected and encoded.

The encoding, in parallel, of the first set of bits and the second set of bits may include solving a linear equation system for computation of the redundancy result such that redundancy bits of each codeword component is encoded by another codeword component.

The encoding, in parallel, of the first set of bits and the second set of bits may include solving a linear equation system for computation of the redundancy result of the encoding of the first set of bits and a second estimated result of the encoding of the second set of bits that do not contradict each other.

The encoding, in parallel, of the first set of bits and the second set of bits may include receiving or generating multiple first estimated results and multiple second estimated results; and finding, out of the multiple first and second estimated results, a pair of first and second estimated results that match outcomes of the encoding of the first set of bits and of the encoding of the second set of bits respectively.

The encoding, in parallel, may include receiving or calculating a syndrome vector (S) which depends on redundancy bits of other component codes and a primitive element matrix (Mr); and creating an equation system for a vector of redundancy bits that represents an output of the encoding of the first and second sets of bits.

The primitive element matrix (Mr) may include first, second, third and fourth sub-matrixes that differ from each other; wherein each one of the first, second, third and fourth sub-matrixes may include powers of a primitive element associated with at least one of the first and second versions.

There may be provided according to an embodiment of the invention a non-transitory computer readable medium that stores instructions that once executed by the computer causes the computer to perform the stages of receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; selecting a first set of bits of the first version and a second set of bits of the second version; encoding, in parallel, the first set of bits and the second set of bits; wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits; and wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.

There may be provided according to an embodiment of the invention a system that may include an encoder and a memory unit; wherein the encoder is arranged to receive or generate a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; select a first set of bits of the first version and a second set of bits of the second version; encode, in parallel, the first set of bits and the second set of bits; wherein an encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits; and wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which

FIG. 1 illustrates a method according to an embodiment of the invention;

FIG. 2 illustrate a codeword according to various embodiments of the invention;

FIG. 3 illustrates a method according to an embodiment of the invention;

FIGS. 4-5 illustrate a two dimensional codeword according to various embodiments of the invention; and

FIG. 6 illustrates a system according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that once executed by a computer result in the execution of the method.

Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that may be executed by the system.

Any reference in the specification to a non-transitory computer readable medium should be applied mutatis mutandis to a system capable of executing the instructions stored in the non-transitory computer readable medium and should be applied mutatis mutandis to method that may be executed by a computer that reads the instructions stored in the non-transitory computer readable medium.

Multi-dimensional encoding invoices receiving or generating multiple versions of a group of bits. The different versions differ from each other by the arrangement of bits. Different versions are associated with different dimensions. For example—assuming that there are two dimensions and that the bits of the group of bits are arranged in a virtual (rectangular) matrix. According to a first arrangement of the bits (first dimension) payloads are formed by the rows of the matrix. According to a second arrangement of the bits (second dimension) payloads are formed by the columns of the matrix. In a non-folded arrangement each payload occupies a single row or column. In a folded arrangement a single payload (of a single codeword component) can occupy more than a single row or column.

Various examples of multi-dimensional encoding are provided in U.S. Pat. Nos. 8,700,970, 8,341,502, 8,621,321, 8,510,639, 8,468,431 and US patent application 20130132793, all being incorporated herein by reference.

Prior art multi-dimensional encoding included serial concatenation, where a dimension is encoded only after another dimension was entirely encoded. This way, the redundancy of one dimension is protected by the other dimension. However, the last dimension may be unprotected. Another prior art (3D application) the each dimension encoding generates a redundancy for codeword components of its dimension, the resulting overall redundancy may then be encoded with another encoder. This type of encoding is not too efficient as the redundancy is protected due to an additional code, and does not take part in the encoding process (like suggested in this invention).

FIG. 1 illustrates method 100 according to an embodiment of the invention.

Method 100 is for parallel multi-dimensional encoding. Method 100 may start by stage 110 of receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit. The first version may be referred to as a first dimension and the second version may be referred to as a second dimension.

Stage 110 may be followed by stage 120 of selecting a first set of bits of the first version and a second set of bits of the second version.

Stage 120 may be followed by stage 130 of encoding, in parallel, the first set of bits and the second set of bits. The encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits. The encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.

The first set of bits may be a part of the first version and the second set of bits may be a part of the second version.

The first set of bits may equal the first version and the second set of bits may equal the second version.

One or more of the first set of bits and the second set of bits may include data bits and does not include redundancy bits.

One or more of the first set of bits and the second set of bits may not include data bits and comprises redundancy bits.

Each one of the first set of bits and the second set of bits may not include data bits and comprises redundancy bits.

The encoding of the second set of bits may be executed by applying an encoding process that is associated with the second set of bits.

One or more of the first and second versions is an interleaved version of the group of bits.

Stages 120 and 130 may be repeated until one, only a part of, or all first sets of bits of the first version are selected and encoded.

Because of the parallel nature of the encoding process the encoding, in parallel, of the first set of bits and the second set of bits may include finding a first redundancy result of the encoding of the first set of bits and a second redundancy result of the encoding of the second set of bits that do not contradict each other.

Stage 130 may include stage 131 of receiving or generating multiple first redundancy results and multiple second redundancy results; and stage 132 of finding, out of the multiple first redundancy results and the multiple second redundancy results, a matching pair of a first redundancy result and a second redundancy result.

The parallel encoding may include stage 133 of receiving or calculating a syndrome matrix (S) and a primitive element matrix (Mr).

Stage 133 may be followed by stage 134 of calculating a vector of redundancy bits that represents an output of the encoding of the first and second sets of bits.

The primitive element matrix (Mr) may include first, second, third and fourth sub-matrixes that differ from each other. Each one of the first, second, third and fourth sub-matrixes may include powers of a primitive element associated with at least one of the first and second versions, to represent the linear encoding operation. Some examples of the sub-matrixes are provided below and are denoted as A1, A2, B and C.

FIG. 2 illustrates two dimensional codeword 201 according to an embodiment of the invention. The two dimensional codeword 201 includes row payloads D1,1-D1,12 210(1,1)-210(1,12) that occupy one row each and include only data bits. It also includes column payloads D2,1-D2,12 220(1,1)-220(1,12) that occupy one row each and include only data bits.

The row payloads and the row redundancies form row codeword components. The column payloads and the column redundancies form column codeword components.

At least some of the row and column redundancies were encoded in parallel to each other.

For example, the first row payload D1,1 210(1,1) and a first column redundancy (“R2,1 240(2,1)) were encoded to provide first row redundancy R1,1 230(1,1) while the first column payload D2,1 220(2,1) and an first row redundancy (R1,1 230(1,1)) were encoded to provide first column redundancy R2,1 240(2,1). This means that codeword components of different dimensions mutually encode the redundancy bits of each other. That is, the codeword component with redundancy R2,1 240 includes D2,1 220 and R1,1 230 as its payload, and the codeword component with redundancy R1,1 230 includes D1,1 210 and R1,1 230 as its payload.

The encoding process may include computation of the redundancies by solving an equation system obtained by inversion of an encoding matrix and multiplication by a syndrome vector, e.g. r=M_R⁻¹·S(r) where M_R is the encoding matrix and S(r) is the syndrome vector, which is computed with the payload bits (note that since a mutual encoding is performed, each codeword payload consists of redundancy bits of the another codeword) both syndrome and encoder matrix can be directly computed from the code definition. It is noted that M_R should be chosen such that it is an invertible matrix.

It is noted that the mentioned above method can be applied on folded codeword components (that span along more than a single row and column) and to more than two dimensions.

It is further noted that the length of the codeword components and/or the code rate may vary between different codeword components.

FIG. 3 illustrates a method 400 for multi-dimensional encoding, according to an embodiment of the invention.

Method 400 may start by stage 410 of encoding multiple versions of a group of bits that correspond to multiple dimensions. Stage 410 may include any stage of method 300. Other encoding schemes may be used.

Stage 410 may be followed by stage 420 of jointly encoding portions of redundancies of a last dimension of the multiple dimensions and portions of redundancies of a not-last dimension to provide joint redundancy.

The joint redundancy may include multiple joint redundancy units, wherein at least one joint redundancy unit is generated by encoding at least a portion of a last dimension redundancy unit and at least a portion of the non-last redundancy portion.

FIGS. 4-5 illustrates two dimensional codeword 200 according to various embodiments of the invention. It includes row payloads D1,1-D1,12 210(1,1)-210(1,12) that occupy one row each and include only data bits. It also includes column payloads D2,1-D2,12 220(1,1)-220(1,12) that occupy one row each and include only data bits.

The row payloads (first dimension, first version) were encoded to provide row redundancies R1,1-R1,12 230(1,1)-230(1,12).

The column payloads (second dimension, second version) were encoded to provide column redundancies R2,1-R2,12 240(2,1)-240(2,12).

FIG. 4 illustrates a joint redundancy R3 250 and R4 260 that include first redundancy units, each is calculated by encoding a single column redundancy, and a second joint redundancy R4 260 that includes second redundancy units, each calculated by encoding a single row. For obtaining joint encoding of R3 250 and R4 260, multiple column redundancy bits (241) are encoded jointly with multiple row redundancy bits 231 in the following way. For column redundancy bits 241 and redundancy bits 261 a redundancy 251 is computed, and for row redundancy bits 231 and redundancy bits 251 a redundancy 261 is computed. That is, the payload corresponding to redundancy bits R3 251 consists of 241 and 261, and the payload corresponding to redundancy bits R4 261 consists of 231 and 251. To compute R3 251 and R4 261 an equation system corresponding to encoder definition is to be computed, as explained earlier by r=M_R⁻¹·S(r).

FIG. 5 illustrates a second joint redundancy encoding of R3 250 and R4 260 that includes first joint redundancy units, each is calculated by encoding a single column redundancy and multiple bits from multiple row redundancies and the other redundancy result 251. For example second joint redundancy unit 261 is calculated by encoding R2,7 240(2,7) and multiple bits (231) from multiple row redundancies and R3 251. At the same time, first joint redundancy unit 251 is calculated by encoding R1,8 230(1,8), multiple bits (241) from multiple column redundancies and R4 261

It is noted that only one of the first and second joint redundancies can be provided, that the encoding can be applied to more than two dimensions and that the encoding may also be responsive to the data bits and not just to the redundancies.

Simultaneous Redundancy Termination

Standard Case

We consider the encoding scheme of the two dimensions.

It is suggested to calculate the redundancies of different dimensions is parallel. This can be done by performing syndrome calculation in a manner that creates the redundancy for multiple dimensions simultaneously.

Per codeword component per dimension, it is possible to calculate the syndrome (as is done during the decoding process) as follows:

S D , i = ∑ j = 0 k D , i ⁢ d D , i ⁡ ( n D , i - j ) · ( α D n D , i - j α D 3 · ( n D , i - j ) α D 5 · ( n D , i - j ) )

Where

a. D Dimension index (½)

b. i Codeword component index within dimension

c. n_D,i Codeword component length for codeword component i of dimension D

d. d_D,i(n_D,i−j) Bit n_D,i−j of codeword component i of dimension D

e. α_D Primitive element of the fields used for dimension D

f. NI_D Number of codeword components in dimension D

g. Q_D Field used in codeword components of dimension D

h. t_D Number of errors corrected per codeword component of dimension D

To calculate the redundancy we stack the binary representation of the syndromes (S_D,i) one on top of the other (for all inner codes within each dimension, for both dimensions) such that

S = ( S 1 , 1 S 1 , 2 ⋮ S 1 , N ⁢ ⁢ I 1 S 2 , 1 S 2 , 2 S 2 , 3 ⋮ S 2 , N ⁢ ⁢ I 2 )

We can now write a linear binary equation that relates between the calculated syndromes and the redundancy as follows:
M_R˜r=S,r=M_R⁻¹˜S

Where r is a bit vector containing the redundancy bits of all the codeword components where the first NI₁·Q₁·t₁ bits correspond to the redundancy of the codeword components of dimension 1 and the last NI₂·Q₂·t₂ correspond to the redundancy of the codeword components of dimension 2.

The matrix M_R is a block diagonal matrix defines by

M R = ( A 1 0 0 0 A 1 0 … 0 0 0 A 1 ⋮ ⋱ ⋮ ⁢ 0 … A 2 0 0 A 2 )

Where there are NI_D binary blocks A_D (D=1,2).

Where

A D = ( α D Q D · t D - 1 … α D 0 α D 3 · ( Q D · t D - 1 ) … α D 3 · 0 α D 5 · ( Q D · t D - 1 ) … α D 5 · 0 )
is represented using the binary representation of each of the primitive value powers.

Serial Encoding

The matrix M_R above yields the standard redundancies, without any simultaneous termination. However, with some modifications to M_R, some more dependencies can be enforced between the redundancies of the two dimensions.

For example, by setting

M ~ R = ( A 1 0 0 0 A 1 0 … B 0 0 A 1 ⋮ ⋱ ⋮ ⁢ 0 … A 2 0 0 A 2 )

We can simulate serial encoding.

That is the case where the codeword components of dimension 1 are encoded after encoding the codeword components of dimension 2 and the payload of dimension 1 codeword components contain some of the redundancy of dimension 2 codes.

FIGS. 4 and 5 show an example of how the bits of an inner are allocated across data payload and redundancy bits.

In this case, we denote by

I_D,i(j) The indexes (j=1, . . . , nr_D,i) of the codeword components redundancy bits of dimension (3−D) that are used in the payload of codeword component i of dimension D.

nr_D,i The number of bits out of the codeword components redundancy bits of dimension (3−D) that are used in the payload of codeword i of dimension D.

The matrix B in the matrix {tilde over (M)}_R is an NI₁·Q₁·t₁×NI₂·Q₂·t₂ binary matrix that is divided into i=1, . . . , NI₁ sub-matrices Q₁·t₁×NI₂·Q₂·t₂ which have none zero columns

( α D Q D · t D + n ⁢ ⁢ r D , i - j α D 3 · ( Q D · t D + n ⁢ ⁢ r D , i - j ) α D 5 · ( Q D · t D + n ⁢ ⁢ r D , i - j ) ) ,
j=1 . . . nr_D,i in locations I_D,i(j) (where D=1).

One method for setting the indexes I_D,i(j) is setting I_D,i(j)=(j+Σ_k=1^i-1nr_D,k). P_D modulo NI_3-D·Q_3-D·t_3-D where P_D is chosen such that it has no common denominators with NI_3-D, j=1 . . . nr_D,i and

n ⁢ ⁢ r D , i = round ( N ⁢ ⁢ I 3 - D · Q 3 - D · t 3 - D N ⁢ ⁢ I D ) ,
i=1 . . . NI_D−1

n ⁢ ⁢ r D , NI D = N ⁢ ⁢ I 3 - D · Q 3 - D · t 3 - D - ∑ k = 1 N ⁢ ⁢ I D - 1 ⁢ n ⁢ ⁢ r D , k

Simultaneous Redundancy Encoding

The matrix {tilde over (M)}_R can be further extended to define simultaneous redundancy encoding of the two dimensions. This would mean the all bits, payload and redundancy are protected by two codes, each from each dimension.

This is done by defining the matrix

M ^ R = ( A 1 0 0 0 A 1 0 … B 0 0 A 1 ⋮ ⋱ ⋮ ⁢ C … A 2 0 0 A 2 )

Where on top of the matrix B we define a similar matrix C (NI₂·Q₂·t₂×NI₁·Q₁·t₁) which is defined similarly to B, except for interchanging the dimensions.

To perform encoding the following calculation should be performed: r={circumflex over (M)}_R⁻¹·S.

It should be noted that if the indexes I_D,i(j) are chosen using the methods defined above, the number P_D for each dimension should be chosen such that {circumflex over (M)}_R is indeed invertible (under GF(2)).

Furthermore, by using the above encoding method, the codeword components become longer and therefore, may become weaker. To limit the impact on the strength of the codeword components, it may be possible make the matrices B and C sparser (for example by setting the number of bits nr_D,i smaller. The result may be that not all redundancy bits are protected by both dimensions.

However, the codeword components will be shorter, making them more powerful.

Joint Redundancy of Redundancy Codes

The calculation of r={circumflex over (M)}_R⁻¹·S(r), from which r is computed by a large equation system may require too much resources as the matrix {circumflex over (M)}_R may be too large, as well as the number of equations to solve a long vector r. Therefore, an alternative approach is depicted in FIGS. 4-5. In this new scheme the two dimensions are encoded as described in the standard case. However, now we encode redundancy of both dimensions jointly. That is, redundancy R1 (redundancy of dimension 1) is jointly encoded with redundancy R2 (redundancy of dimension 2). The encoding is done in a manner that simultaneously calculates the redundancies as described in the method above. However, now the inverse matrix will be much smaller since it will include fewer codeword components.

FIG. 6 illustrates a system 600 for multi-dimensional encoding, according to an embodiment of the invention. The system 600 includes a memory unit 640 and a memory controller 620 that includes an encoder 610. The encoder 610 can perform any method illustrated in the specification. The memory controller 620 can control the storage of the codewords at the memory unit 640, can retrieve the codewords and decode then to extract data.

It is noted that the decoding process may be done in various manners. The decoding can also be interleaved.

Non-limiting examples of decoding include:

• • a. Irregular multi-dimensional decoding (using codeword components of different size and/or different rate).
  • b. Using soft decoding with list decoding.
  • c. Applying hard and/or soft decoding with false correction elimination (FCE) methods.
  • d. Performing hard decoding with intersections decoding.

The invention may also be implemented in a computer program for running on a computer system, at least including code portions for performing steps of a method according to the invention when run on a programmable apparatus, such as a computer system or enabling a programmable apparatus to perform functions of a device or system according to the invention. The computer program may cause the storage system to allocate disk drives to disk drive groups.

A computer program is a list of instructions such as a particular application program and/or an operating system. The computer program may for instance include one or more of a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.

The computer program may be stored internally on a non-transitory computer readable medium. All or some of the computer program may be provided on computer readable media permanently, removably or remotely coupled to an information processing system. The computer readable media may include, for example and without limitation, any number of the following magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.

A computer process typically includes an executing (running) program or portion of a program, current program values and state information, and the resources used by the operating system to manage the execution of the process. An operating system (OS) is the software that manages the sharing of the resources of a computer and provides programmers with an interface used to access those resources. An operating system processes system data and user input, and responds by allocating and managing tasks and internal system resources as a service to users and programs of the system.

The computer system may for instance include at least one processing unit, associated memory and a number of input/output (I/O) devices. When executing the computer program, the computer system processes information according to the computer program and produces resultant output information via I/O devices.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. Also, plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.

Although specific conductivity types or polarity of potentials have been described in the examples, it will be appreciated that conductivity types and polarities of potentials may be reversed.

Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein may be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

Furthermore, the terms “assert” or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.

Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.

Also for example, the examples, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type.

Also, the invention is not limited to physical devices or units implemented in non-programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code, such as mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices, commonly denoted in this application as ‘computer systems’.

However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.