Herzelia
Israel
68
2020-04-21
The entities that hold a legal rights for patent applications filed by inventor WEINGARTEN Hanan:
Hanan WEINGARTEN from Herzelia, IL has applied for patents for these inventions. The list has both pending applications and granted patents:
Multi-dimensional decoding
#2 | 2019-05-28System and method for encoding using multiple linear feedback shift registers
#3 | 2018-11-06Programming an embedded flash storage device
#4 | 2018-04-24Fast decoding of data stored in a flash memory
#5 | 2017-12-26Flash memory chip processing
#6 | 2017-02-28Interleaved encoding
#7 | 2017-01-10Error correction
#8 | 2017-01-03Digital signaling processing for three dimensional flash memory arrays
#9 | 2016-12-20Flash memory cells wear reduction
#10 | 2016-12-20Codeword management
#11 | 2016-11-22Management of a non-volatile memory module
#12 | 2016-09-20Power management
#13 | 2016-08-30System, method and computer program product for processing read threshold information and for reading a flash memory module
#14 | 2016-08-02Parallel encoding method and system
#15 | 2016-07-19System and method for irregular multiple dimension decoding and encoding
#16 | 2016-06-21Advanced management of a non-volatile memory
#17 | 2016-02-02False error correction detection
#18 | 2015-11-24Advanced management of a non-volatile memory
#19 | 2015-03-31System and methods for dynamic erase and program control for flash memory device memories
#20 | 2015-03-31System, method and computer readable medium for generating soft information
#21 | 2015-03-31System and method for flash memory management
#22 | 2015-03-24System, method and computer program product for joint search of a read threshold and soft decoding
#23 | 2014-12-11SYSTEMS AND METHODS FOR ERROR CORRECTION AND DECODING ON MULTI-LEVEL PHYSICAL MEDIA
#24 | 2014-11-04System, method and computer program product for processing read threshold information and for reading a flash memory module
#25 | 2014-09-16Methods, systems and computer readable medium for writing and reading data
#26 | 2014-06-24Systems and methods for handling immediate data errors in flash memory
#27 | 2013-11-19System, method and computer program product for programming and for recovering from a power failure
#28 | 2013-09-12Systems and methods for temporarily retiring memory portions
#29 | 2013-08-29Advanced management of a non-volatile memory
#30 | 2013-08-15State responsive operations relating to flash memory cells
#31 | 2013-04-25Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
#32 | 2013-03-28Physical levels deterioration based determination of thresholds useful for converting cell physical levels into cell logical values in an array of digital memory cells
#33 | 2012-12-06System and method for managing a non-volatile memory
#34 | 2012-09-20Obtaining soft information using a hard interface
#35 | 2012-08-23Devices and method for wear estimation based memory management
#36 | 2012-06-07Interleaving codeword portions between multiple planes and/or dies of a flash memory device
#37 | 2012-05-03Method, system and computer readable medium for copy back
#38 | 2012-03-15Systems and methods for averaging error rates in non-volatile devices and storage systems
#39 | 2012-03-15System and method for adjusting read voltage thresholds in memories
#40 | 2012-03-01System and method for accelerated sampling
#41 | 2012-01-12SYSTEMS AND METHODS FOR STORING, RETRIEVING, AND ADJUSTING READ THRESHOLDS IN FLASH MEMORY STORAGE SYSTEM
#42 | 2012-01-12Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system
#43 | 2012-01-05System and method for data recovery in multi-level cell memories
#44 | 2011-12-08Method, system and medium for analog encryption in a flash memory
#45 | 2011-10-13System and method for storing information in a multi-level cell memory
#46 | 2011-10-06Method, system and medium for analog encryption in a flash memory
#47 | 2011-09-01System and method for multi-dimensional decoding
#48 | 2011-09-01System and method for multi-dimensional decoding
#49 | 2011-06-30System and method for setting a flash memory cell read threshold
#50 | 2011-05-19System and method for uncoded bit error rate equalization via interleaving
#51 | 2011-04-28Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages
#52 | 2011-03-03Systems and methods for pre-equalization and code design for a flash memory
#53 | 2010-11-18Systems and method for flash memory management
#54 | 2010-10-07Compact chien-search based decoding apparatus and method
#55 | 2010-10-07Encoding method and system, decoding method and system
#56 | 2010-08-19Systems and methods for error correction and decoding on multi-level physical media
#57 | 2010-08-19Systems and methods for averaging error rates in non-volatile devices and storage systems
#58 | 2010-08-19Systems and methods for determining logical values of coupled flash memory cells
#59 | 2010-08-05Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
#60 | 2010-07-15Flash memory device with physical cell value deterioration accommodation and methods useful in conjunction therewith
#61 | 2010-06-10Methods for adaptively programming flash memory devices and flash memory systems incorporating same
#62 | 2010-05-27Low power chien-search based BCH/RS decoding system for flash memory, mobile communications devices and other applications
#63 | 2010-05-27Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith
#64 | 2010-05-13Systems and methods for handling immediate data errors in flash memory
#65 | 2010-04-15Reprogramming non volatile memory portions
#66 | 2010-04-08Systems and methods for multiple coding rates in flash devices
#67 | 2010-03-11Flash memory apparatus with a heating system for temporarily retired memory portions
#68 | 2010-03-04Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications
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