CHIP MODULE HAVING CONTACT SURFACE WITH DUAL-LAYER PROTECTIVE COATING

Description

TECHNICAL FIELD

The present disclosure relates to a chip module and to a process for producing a chip module.

BACKGROUND

Owing to steadily rising precious metal prices, it is commercially desirable to reduce a layer thickness of a final gold (Au) plating layer on chip card modules to a minimum. However, a protective effect of Au plating layers decreases with thickness. It has therefore not been possible to date to use thin Au plating layers (for example with a thickness of less than 0.02 μm) for applications in the field of bank and identity verification (ID) cards with their requirements for salt mist testing according to ISO/IEC 7810 and chemical stability according to ISO/IEC 10373-1.

In addition, the galvanically deposited gold in thin layers (for example with a thickness of less than 0.02 μm) loses its golden color, and the grayish nickel layer beneath becomes visible. The surface of the module has a yellowish-silver appearance and no longer has the pronounced gold color appreciated by the customer. This lowers market acceptance.

For those reasons, it is currently necessary to accept either the higher cost for the thicker Au coating or lower quality in terms of appearance and corrosion resistance.

BRIEF DESCRIPTION

A chip module is provided. The chip module has a contact surface for contact-based communication with a reader, where the contact surface includes a metal, and a coating of the contact surface with a double layer composed of a lower layer of an organic silicon compound and/or a carbon compound and an upper layer of silicon oxide, wherein the double layer has a thickness that has an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 when measured in accordance with ISO 10373-1.

A person skilled in the art will discern further features and advantages of the invention upon reading the following detailed description and examining the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is shown in an exemplary and non-limiting manner in the illustrations of the attached drawings, in which identical reference numbers refer to similar or identical elements. The elements in the drawings are not necessarily depicted to scale in relation to each other. The features of the various examples shown can be combined, provided that they are not mutually exclusive.

FIG. 1 shows a schematic cross-sectional view of a chip module (integrated as an overview in a chip card and as a cut-out magnification) according to various working examples during contact-based operation;

FIG. 2 shows photographs for comparison of contact surfaces of the chip module according to various working examples and contact surfaces of chip modules according to the prior art; and

FIG. 3 shows a flow diagram of a process for producing a chip module according to various working examples.

DETAILED DESCRIPTION

A current Infineon solution is a gold layer (Au layer) with a thickness of more than 0.03 μm in combination with an organic coating. The organic coating is what is called a called self-assembly monolayer (SAM) in which the sulfur head group of a surfactant molecule binds to the Au surface. This was chosen to provide optimal protection in salt mist tests, gas tests and an in-house test to simulate the inside of a wallet. This combination led to higher performance in terms of corrosion resistance compared to competitors. This has been shown by specification tests and practical use. Competitors such as Linxens and Agencomm have developed similar combinations in recent years.

As the Au thickness of the galvanic layer decreases, the protective effect of this coating also decreases, since the more porous gold layer offers fewer binding partners for the coating molecules.

The working examples described here enable application of thin Au layers (<0.02 μm) to chip card modules, preserving both the excellent corrosion protection and the valuable gold color possessed by the standard Au layers (with a thickness of more than 0.03 μm).

In various working examples, this is achieved by applying a double protective layer on top of the Au coating. The double protective layer consists of two different coatings that complement one another in terms of their corrosion protection performance. The top layer is a plasma-deposited SiO₂coating (Si oxide+short-chain aliphatics, thickness about 80 nm), which is applied to an organic self-assembly monolayer (SAM).

As a second effect in addition to the protective function, the SiO₂ layer creates a yellow-gold interference color that gives the surface a pale gold appearance.

This is illustrated in FIG. 2. Even though the grayscale representation of the original color photographs is incapable of reproducing the golden gloss, it is also apparent from the grayscale representation that an appearance of the chip module 101 shown in the middle according to various working examples (or of several chip modules 101) resembles that of the chip module 201 according to the prior art as shown on the left, which has a final gold layer having a thickness of 30 nm or more.

The appearance of the comparative example of a chip module 220 on the right, in which the gold layer has a thickness of less than 20 nm and in which no silicon oxide layer is applied on top of the SAM layer, by contrast, has a darker and matter appearance even in the grayscale representation.

FIG. 1 shows, at the top, a schematic cross-sectional view of a chip card 100 with a chip module 101 integrated in a chip card body 114 according to various working examples, which, for contact-based operation, has a contact surface 102 (which may in turn have a multitude of contact surface areas that may be insulated from one another, for example for provision of an operating voltage with different polarities, different signals, etc.). The diagram shows the chip card 100 or the chip module 101 during contact-based operation, i.e. while a part of a reader 106 is making contact with the contact surface.

The chip card 100 may be formed as a pure contact-based chip card, or for example as a dual-interface chip card set up for both contact-based operation and contactless operation.

FIG. 1, at the bottom, shows a detail enlargement of the upper diagram (the chip 110 is omitted at the bottom for clarity), which in particular shows a working example of the contact surface 102 and its coating in detail.

The chip module 101 may include a chip 110, for example, a semiconductor chip, for example a chip 110 which is set up for typical chip card use, e.g. payment transactions, identification/authentication, or the like.

The chip 110 may be coupled, for example in a manner essentially known to the person skilled in the art, to the contact surface 102 which includes a metal. For example, the metal may include a base metal because this can optimize cost savings through the protective layer. However, in various working examples, precious metals can also appropriately be provided with the coating, because this can make it possible, for example, to form a thinner precious metal layer.

The contact surface 102 may be made of a single metal, a layer stack composed of different metals or a metal alloy. The metal of the electrically conductive region may include or consist of, for example, a copper-tin-zinc alloy, gold, palladium, copper, nickel, copper-nickel or an alloy of the above metals. The top layer of metal may include gold or consist of gold.

In FIG. 1, the contact surface 102 is formed by way of example from a layer stack of three metal layers: a (copper) carrier layer 102a which may, for example, have a thickness within a range from about 13 μm to about 35 μm, atop the carrier layer 102a an intermediate (nickel) layer 102b which may have a thickness of about 1 μm to about 2 μm, and atop the intermediate layer 102b an outer layer 102c which may include, for example, gold, palladium or a copper-tin-zinc alloy. The outer layer 102c may, for example, have a thickness within a range from about 8 nm to about 300 nm.

According to various working examples, the outer layer 102c may have a thickness of less than 20 nm, for example within a range from about 8 nm to less than 20 nm.

The contact surface 102 may be formed in various working examples on a carrier material 112, for example a carrier strip typically utilized in the production of chip modules, which may be formed, for example, from polyimide, polyethylene terephthalate (PET) or an epoxy material. A typical thickness of the carrier material 112 may be within a range from about 25 μm to about 200 μm.

The chip module 101 may also have a coating of the contact surface 102 having a lower layer 104u of at least one organic silicon compound and/or a carbon compound and having an upper layer 1040 of silicon oxide (SiO₂) disposed thereon.

The lower layer 104u and the upper layer 1040 may collectively be referred to as double layer 104 or layer 104 for short.

The double layer 104 may have a thickness that has an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 when measured in accordance with ISO 10373-1.

This means that the arrangement of the double layer 104 comprises two actually dielectric materials (namely the material of the lower layer 104u, if it is the dielectric organic silicon compound, and the silicon oxide of the upper layer 1040) are applied sufficiently thinly, for example with a layer thickness within a range from about 10 nm to about 200 nm, for example between about 20 nm and about 100 nm, for example between about 20 nm and about 50 nm, that surface contact resistance is still sufficiently small to enable contact-based communication by means of the electrically conductive region 102. In particular, the electrical surface contact resistance may be not more than 500 mΩ.

In various working examples, a thickness of the upper layer 104o within a range between about 75 nm and about 85 nm, for example roughly or exactly 80 nm, may be selected, because this makes it possible to exploit a property of the silicon oxide:

Because of differences in refractive index between the silicon oxide and air, the upper layer creates 104o interference colors depending on the layer thickness. At the applied layer thickness of about 80 nm (+/−5 nm), the applied layer produces a yellowish-golden interference colour which causes the surface to have a pale gold appearance, and hence similar to the appearance of a thicker gold layer.

In various working examples in which the upper layer 1040 has the described layer thickness of about 80 nm (+/−5 nm) or a different layer thickness, the chip module 101 may have higher corrosion resistance in various working examples.

The SAM that can be utilized for the lower layer 104u is a monomolecular layer of surfactant molecules with a sulfur-containing head group and has a typical thickness of a few angstroms. The sulfur is capable of coordinative binding to the Au atoms but has low affinity to oxides. The sulfur can provide a good protective function against the conditions of the SM test (ISO/IEC 7810), but its effect may decrease slightly with thinner Au layers 102c, since the Au layer 102c can become porous and oxides of a metal beneath (e.g. nickel) appear on the surface.

The upper layer 1040 (the SiO₂ layer) deposited on the lower layer 104u (for example directly thereon, such that the upper layer 1040 and the lower layer 104u form a common interface) can effectively bind to the oxides on the surface (and also to the side chains of the SAM) and form excellent resistance to corrosive chemicals such as SO₂, H₂S, NOx and Cl₂, but is impaired in the salt mist test.

Under the conditions of the SM test, the upper layer 1040 acts as a sacrificial layer, delaying the attack of the chemicals. The underlying lower layer 104u (SAM coating), on the other hand, can show good performance in the salt mist test. The combination of the two coatings is better than each on its own.

The at least one electrically conductive region may, in various working examples, have an Rz surface roughness within a range from about 0.1 to about 6 μm, for example between about 0.5 μm and 3 μm. As illustrated in FIG. 1, this may, for example, have the effect that the thickness of the layer 104 is slightly nonuniform, such that electrical resistance between the reader and the electrically conductive region 104 is reduced, for example, in the region of a “mountain”.

“Organic silicon compound”, also referred to organosilicon compound, is a collective term for compounds that either have direct silicon-carbon bonds (Si—C) or in which the carbon is joined to the silicon via oxygen, nitrogen or sulfur atoms. Organosilicon compounds can be described by the general formula RnSiX4-n (with n from 1 to 4) where R represents various organic radicals, for example aliphatic, aromatics, heterocycles, and X represents different groups, e.g. OH, Si—O, Si—N, Si—C, Cl, H, etc.

Examples of organosilicon compounds that are usable for layer 104 are organosilane, organosilanol, organochlorosilane, siloxane, silicone, polysilazane and carbosilane.

FIG. 3 shows a flow diagram 300 of a process for producing a chip card according to various working examples.

The process comprises coating a contact surface for contact-based communication with a reader including a metal with a lower layer of an organic silicon compound and/or a carbon compound (310), and coating the lower layer with an upper layer of silicon oxide, wherein the double layer of the lower and upper layer has a thickness that has an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 when measured in accordance with ISO 10373-1 (320).

The contact surface can be coated with the lower layer in various working examples by means of wet-chemical coating by means of immersion, free-jet plasma coating, chemical vapor deposition, hot-wire-activated vapor deposition or physical vapor deposition.

The lower layer can be coated with the upper layer in various working examples by means of wet-chemical coating by means of plasma coating.

There follows a summary of a few working examples.

Working example 1 is a chip module. The chip module has a contact surface for contact-based communication with a reader, where the contact surface includes a metal, and a coating of the contact surface with a double layer composed of a lower layer of an organic silicon compound and/or a carbon compound and an upper layer of silicon oxide, wherein the double layer has a thickness that has an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 when measured in accordance with ISO 10373-1.

Working example 2 is a chip module according to working example 1, wherein the contact surface includes a gold layer as the top metal layer that forms a common interface with the bottom layer.

Working example 3 is a chip module according to working example 2, wherein the gold layer has a layer thickness within a range of less than 20 nm, for example within a range from about 10 nm to less than 20 nm.

Working example 4 is a chip module according to any of working examples 1 to 3, wherein the upper layer has a layer thickness within a range from about 75 nm to about 85 nm, for example of about 80 nm.

Working example 5 is a chip module according to any of working examples 1 to 4, wherein the upper layer has been produced by means of plasma coating.

Working example 6 is a chip module according to any of working examples 1 to 5, wherein the double layer has a layer thickness within a range from about 90 nm to about 200 nm.

Working example 7 is a chip module according to any of working examples 1 to 6, wherein the lower layer has been produced by means of a coating process from a group of coating processes, wherein the group comprises: wet-chemical coating by immersion, free-jet plasma coating, chemical gas phase deposition, hot-wire-activated gas phase deposition and physical gas phase deposition.

Working example 8 is a chip module according to any of working examples 1 to 7, wherein the at least one organic silicon compound includes at least one compound selected from a group consisting of: Si—O, Si—N, Si—C, Si—OH and Si—H.

Working example 9 is a chip module according to any of working examples 1 to 8, wherein the at least one organic silicon compound includes at least one compound selected from a group consisting of: organosilane, organosilanol, organochlorosilane, siloxane, silicone, polysilazane and carbosilane, and/or wherein the at least one carbon compound includes at least one compound selected from a group consisting of: amorphous carbon, diamond, graphene and graphite.

Working example 10 is a process for producing a chip module. The process comprises coating a contact surface for contact-based communication with a reader including a metal with a lower layer of an organic silicon compound and/or a carbon compound, and coating the lower layer with an upper layer of silicon oxide, wherein the double layer of the lower and upper layer has a thickness that has an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 when measured in accordance with ISO 10373-1.

Working example 11 is a process according to working example 10, wherein the contact surface includes a gold layer as the top metal layer that forms a common interface with the bottom layer.

Working example 12 is a process according to working example 11, wherein the gold layer has a layer thickness within a range of less than 20 nm, for example within a range from about 10 nm to less than 20 nm.

Working example 13 is a process according to any of working examples 10 to 12, wherein the upper layer has a layer thickness within a range from about 75 nm to about 85 nm, for example of about 80 nm.

Working example 14 is a process according to any of working examples 10 to 13, wherein the upper layer has been produced by means of plasma coating.

Working example 15 is a process according to any of working examples 10 to 14, wherein the double layer has a layer thickness within a range from about 90 nm to about 200 nm.

Working example 13 is a process according to any of working examples 10 to 15, wherein the lower layer has been produced by means of a coating process from a group of coating processes, wherein the group comprises: wet-chemical coating by immersion, free-jet plasma coating, chemical gas phase deposition, hot-wire-activated gas phase deposition and physical gas phase deposition.

Working example 13 is a process according to any of working examples 10 to 16, wherein the at least one organic silicon compound includes at least one compound selected from a group consisting of: Si—O, Si—N, Si—C, Si—OH and Si—H.

Working example 13 is a process according to any of working examples 10 to 17, wherein the at least one organic silicon compound includes at least one compound selected from a group consisting of: organosilane, organosilanol, organochlorosilane, siloxane, silicone, polysilazane and carbosilane, and/or wherein the at least one carbon compound includes at least one compound selected from a group consisting of: amorphous carbon, diamond, graphene and graphite.

It should be pointed out that the description and the drawings only illustrate the principles of the proposed methods and devices. A person skilled in the art will be capable of implementing different arrangements which, although they are not expressly described or shown here, embody the principles of the invention and are included within the scope thereof. In addition, all examples and embodiments outlined in the present document are intended fundamentally and expressly for explanatory purposes only, in order to help the reader understand the principles of the proposed processes and devices. In addition, all statements in this document that describe principles, aspects and embodiments of the invention and specific examples thereof are also intended to encompass their equivalents.